A register behind a clock MUX sees multiple clocks. Is that always an error?
From PDVerse PnR Interview Handbook · pdVerse Mentor Guide
Short Answer
It may be valid across modes, but within one scenario the MUX selection and exclusivity must reflect functional reality; ambiguity is a hard stop.
Technical Explanation
Multiple clocks at one register pin may describe valid mode choices, or it may mean ICC2 sees two clocks active at once. The mode and MUX selection decide which interpretation is correct.
What To Check
• Warning sign: check_timing reports multiple_clock at the downstream register. • Inspect: Keep at least two possible causes open, then use one named object and the active mode or scenario to separate them. • Correct: Inspect case analysis, clock groups, mode SDC, and MUX connectivity; obtain functional/STA ownership for exclusivity intent.
Command Checks & Actions
• check_timing -include {multiple_clock}: finds missing or inconsistent timing setup
• report_case_analysis: shows constants applied for the active mode
• report_clocks: shows clock definitions and relationships
• report_exceptions: shows timing exceptions and their scope
Run the commands in order. Each line answers a separate part of the check.Healthy, Suspicious & Hard-stop Results
• Expected: It may be valid across modes, but within one scenario the MUX selection and exclusivity must reflect functional reality; ambiguity is a hard stop. • Investigate: check_timing reports multiple_clock at the downstream register. • Stop before floorplanning when required logic or timing coverage is missing or unexplained. Inspect case analysis, clock groups, mode SDC, and MUX connectivity; obtain functional/STA ownership for exclusivity intent.
Common Mistake
Do not assume the check passed just because ICC2 continued: check_timing reports multiple_clock at the downstream register. Fix or narrowly justify the named objects, then rerun the same command.
What The Interviewer Is Testing
Be ready to explain why this matters before floorplanning: check_timing reports multiple_clock at the downstream register.
Follow-up Question & Model Response
Model response: “I would save the report, inspect one affected object in the correct block and scenario, and make or request this correction: Inspect case analysis, clock groups, mode SDC, and MUX connectivity; obtain functional/STA ownership for exclusivity intent. Then I would reopen the clean checkpoint and rerun the same evidence.”
Practical Example
Symptom: check_timing reports multiple_clock at the downstream register. Corrective path: Inspect case analysis, clock groups, mode SDC, and MUX connectivity; obtain functional/STA ownership for exclusivity intent.
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