Level 4 · Signoff Reasoning

Expert PnR Interview Questions

Master scenario-based readiness decisions, conflicting evidence triage, floorplan DRC/congestion closure, and proceed-or-stop reviews.

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What to practise at this level

Master scenario-based readiness decisions, conflicting evidence triage, floorplan DRC/congestion closure, and proceed-or-stop reviews.

  1. 91 Thousands of registers show no_clock after SDC load. What do you do?Expert · Treat this as a hard stop and test competing causes: wrong current mode, empty clock source selector, broken generated/gated path, or mismatched hierarchy.
  2. 92 A generated clock exists by name but has no valid path from its master. How do you diagnose it?Expert · The name proves object creation only; inspect master, source, target, transformation, case analysis, disabled arcs, and real netlist connectivity.
  3. 93 Why can a very low unconstrained-endpoint count coexist with poor coverage?Expert · False paths, case analysis, disabled arcs, inactive scenarios, or missing clocks can remove paths before they become unconstrained endpoints.
  4. 94 Timing becomes clean after a broad false path. What is the correct response?Expert · Assume the improvement is unproven until exact membership and functional justification show that only impossible paths were removed.
  5. 95 A case-analysis constraint removes many paths. How do you decide whether it is valid?Expert · Correlate the constant with the active functional mode, source object, MUX behaviour, clocks, and disabled arcs.
  6. 96 A register behind a clock MUX sees multiple clocks. Is that always an error?Expert · It may be valid across modes, but within one scenario the MUX selection and exclusivity must reflect functional reality; ambiguity is a hard stop.
  7. 97 How do you triage a combinational loop before floorplanning?Expert · Distinguish an intentional feedback model from an accidental netlist loop and identify any automatic timing-arc break chosen by the tool.
  8. 98 Ignored exceptions appear in the report. What does that mean?Expert · An exception may be overridden, redundant, malformed, or dominated by another constraint; its presence in SDC does not mean it affects analysis.
  9. 99 Setup improves after a multicycle exception but hold becomes strange. Why?Expert · The functional setup-cycle shift and corresponding hold relationship were not derived consistently from launch/capture edges.
  10. 100 A disabled timing arc removes a clock path. How do you find ownership?Expert · Determine whether the disable comes from a library model, user constraint, case analysis, loop breaking, or mode-specific condition.
  11. 101 Functional constraints were loaded into test mode. What evidence exposes it?Expert · Compare scenario-mode associations, clocks, case analysis, I/O delays, and exception membership across modes.
  12. 102 One required mode/corner combination is missing. Can floorplanning start?Expert · If the missing scenario can change logical/timing readiness or design assumptions, it is a hard stop until the coverage matrix is restored.
  13. 103 How do you compare functional and test-mode readiness?Expert · Compare clocks, constants, I/O constraints, exceptions, active checks, and expected sequential populations separately; neither mode substitutes for the other.
  14. 104 ICC2 and PrimeTime disagree. How do you test a unit hypothesis?Expert · Compare reported units and the same clock, delay, slew, and load values before comparing slack; keep each tool's logs separate.
  15. 105 How do you test whether ICC2 and PrimeTime use different libraries?Expert · Compare resolved library versions, PVT, operating conditions, cell identities, and scenario mapping before path arithmetic.
  16. 106 How do you correlate clock differences between ICC2 and PrimeTime?Expert · Compare clock creation, generated relationships, waveform, latency, uncertainty, case analysis, and mode scope without mixing command outputs.
  17. 107 A bulk input-delay command constrained the clock port. What is the impact?Expert · It models the clock port as ordinary data and can create misleading boundary paths or constraints; selector scope is defective.
  18. 108 A negative output minimum delay appears. Is it automatically wrong?Expert · No; the sign can follow the receiving interface hold convention, but it must be derived and associated with the correct clock and edge.
  19. 109 Many constraints target objects optimised away by synthesis. Who owns the fix?Expert · The applied SDC must match the delivered netlist; mapping may need synthesis/STA regeneration, not local wildcard repair by PD.
  20. 110 How do you approve an intentional undriven or unloaded object?Expert · Require named-object evidence, functional reason, affected modes, owner, risk, and a rerun-stable waiver; never waive only a message count.
  21. 111 A macro remains a black box one day before floorplanning. Proceed or stop?Expert · Stop unless the approved abstraction and next-stage interface requirements are complete and the project explicitly accepts that model state.
  22. 112 Why is zero reported timing violations insufficient for readiness?Expert · Slack covers only analysed paths in active scenarios; missing clocks, exceptions, constants, inactive modes, or absent paths can make the result artificially clean.
  23. 113 Must every sanity warning be zero?Expert · No; each warning must be classified as a defect or justified intent with named objects, evidence, owner, risk, and review date.
  24. 114 When should PD return the handoff instead of editing locally?Expert · Return defects in functional connectivity, synthesis structure, library release, interface timing intent, or mode definitions to their authoritative owner.
  25. 115 How do you make the final proceed-or-stop decision?Expert · Proceed only when provenance matches, linking resolves, structure is classified, SDC semantics are reviewed, clocks/I/O/exceptions/scenarios provide intended coverage, and waivers are owned and reproducible.
  26. 171 All floorplan legality checks pass, but congestion is unacceptable. What do you do?Expert · Treat legality and quality separately. Keep the legal baseline, identify the hot spot’s demand and capacity causes, change the smallest responsible physical choice, and rerun the same estimate.
  27. 172 Average utilisation is good, but one region is locally impossible. How do you prove it?Expert · Measure usable local area after rows, halos, blockages, voltage areas, and fixed objects, then compare with the cell and routing demand assigned there.
  28. 173 Two equal-area aspect ratios disagree on timing and congestion. Which wins?Expert · Use a scorecard with identical definitions and methods. Choose the shape whose combined row usability, macro legality, channels, pin access, PG reservation, congestion, timing, and change risk best matches project priorities.
  29. 174 A macro array is legal, but its allowed orientations create pin-access failure. How do you respond?Expert · Do not force an illegal orientation. Test legal orientations, spacing, staggering, array order, pin-facing strategy, and surrounding routing layers; then change the array geometry if access remains impossible.
  30. 175 A macro channel routes before PG reservation but fails after straps are planned. What is the correct fix?Expert · The original channel capacity estimate was incomplete. Recalculate usable signal tracks after PG widths, spacing, vias, and blockages, then negotiate macro spacing, strap placement, pin access, or layer allocation.
  31. 176 One macro has a huge halo; another has pin-access failure from a small halo. How do you size them?Expert · Use asymmetric, evidence-based margins where supported: reserve space where pins, vias, routing, or optimisation cells need it, and avoid wasting quiet sides.
  32. 177 Boundary or corner cells are missing or wrongly oriented around a voltage area. What do you check?Expert · Check voltage-area geometry, row orientation, inside versus outside corners, library-specific rules, legal cell orientations, and whether the correct insertion flow ran.
  33. 178 Fixed package pins fight the logical dataflow. What can floorplanning change?Expert · Treat package pins as constraints, then adapt macro locations, block pins, feedthroughs, aspect ratio, and routing corridors around them. Escalate only when the package interface itself is negotiable.
  34. 179 A feedthrough improves top-level timing but harms the block interface. How do you decide?Expert · Compare top-level delay saved with block pin count, alignment, route capacity, buffering, voltage-area compatibility, reuse, and ECO flexibility. The system owner and block owner must agree.
  35. 180 A block pin is legal but off-track, stacked, or on an unusable layer. What is the response?Expert · Treat this as a pin-access defect. Report the pin geometry and nearby tracks/resources, then move, spread, reorder, or re-layer it within the interface constraints.
  36. 181 Congestion becomes severe only after PG-resource reservation. What does that prove?Expert · It proves the earlier signal-only model was incomplete, not that power planning should be ignored. Rebalance shared routing resources and floorplan geometry.
  37. 182 A voltage-area boundary strands cells or creates an unusable sliver. How do you diagnose it?Expert · Compare assigned cell area and growth with legal rows, guard bands, enclosure, boundary cells, switch/interface-cell zones, macro overlap, and supply access.
  38. 183 Early timing improves while congestion worsens. How do you choose the next move?Expert · Identify which named paths improved and which local resources failed, then test a change that preserves the timing benefit while relieving concentrated demand.
  39. 184 Two engineers report different results for the same floorplan. How do you isolate the cause?Expert · Compare floorplan write-out, checkpoint, tool version, app options, scenarios, libraries, constraints, placement seed, PG/blockage assumptions, and report settings before comparing numbers.
  40. 185 initialize_floorplan produces an invalid or unexpected boundary. What do you check?Expert · Check control type, shape, side lengths or ratios, boundary points, orientation, offsets, retained objects, site definition, and whether an old boundary was intentionally kept.
  41. 186 A macro is inside the core but off-grid or illegally oriented. Is this a minor warning?Expert · No. It can break manufacturing/block-grid requirements, pin access, array alignment, or power connectivity; treat it as a hard stop for that macro placement.
  42. 187 Power or pin checks report missing or wrong routing tracks. How do you proceed?Expert · Confirm technology-layer definitions, preferred directions, pitch, offset, width, core coverage, restrictions, and whether tracks were intentionally regenerated. Do not create arbitrary tracks to silence the check.
  43. 188 Macros overlap or extend outside the parent boundary after refinement. What is the correct debug path?Expert · Check stale constraints, fixed status, orientation-dependent dimensions, snap movement, relative-location constraints, voltage areas, and which floorplan version was loaded.
  44. 189 Rows remain under macros or blockages. Why is that dangerous?Expert · They inflate nominal placeable area and can mislead early placement, utilisation, or legality. Determine whether the rows should be cut, made transparent by methodology, or associated differently.
  45. 190 Pin constraints conflict with routing blockages or PG shapes. Who owns the fix?Expert · Identify whether package/interface intent, block pin constraints, routing blockage, or PG reservation is authoritative, then negotiate a geometry that preserves the required function.
  46. 191 check_feedthroughs reports unused, reused, and constraint violations together. How do you triage them?Expert · Separate classifications, inspect named nets and blocks, and compare each with intended topology, pin pairs, buffering, and reuse policy. The categories require different decisions.
  47. 192 The floorplan has no credible space for the proposed power grid. Can macro placement proceed?Expert · Stop or iterate if required PG sources, rings/straps/rails, macro pin access, switch corridors, or via paths cannot fit without destroying signal capacity. Planning must reserve these resources first.
  48. 193 A critical path detours around a macro despite acceptable centre-to-centre distance. What should you inspect?Expert · Inspect actual macro pin sides, route corridor, blockages, voltage areas, feedthrough options, hierarchy crossings, congestion, and buffering sites. Centre distance can hide a long legal path.
  49. 194 How do you compare two floorplans without cherry-picking metrics?Expert · Use one scorecard with declared definitions and identical methods for area/utilisation, usable rows, macro legality, channels, pins, congestion, PG reservation, voltage areas, early timing, and change risk.
  50. 195 How do you make the final floorplan proceed, iterate, waive, or return decision?Expert · Proceed only when boundaries, rows, macros, channels, pins, feedthroughs, tracks, PG reservation, voltage areas, congestion, and early timing are physically credible and reproducible. Iterate quality risks, waive only justified intent, and return upstream defects to their owner.