IntermediateQuestion 77 of 84Source PDF page undefined

How do you prove clocks reach sequential clock pins?

From PDVerse PnR Interview Handbook · pdVerse Mentor Guide

Short Answer

Use no_clock checks and targeted timing reports to correlate expected register groups with clock propagation through logical arcs.

Technical Explanation

Treat this as a readiness check. It should produce named objects and a result that another engineer can repeat from the same handoff.

What To Check

• Warning sign: A primary clock is reported, yet a gated branch or generated domain never reaches its registers. • Inspect: Compare one named object across the related reports; the same object should tell a consistent story. • Correct: Repair clock/gating/generated-clock intent or netlist connectivity, then compare affected register groups.

Command Checks & Actions

• check_timing -include {no_clock gated_clock}: finds missing or inconsistent timing setup • report_timing -to <register_clock_pin>: shows a path and its timing calculation Run the commands in order. Each line answers a separate part of the check.

Healthy, Suspicious & Hard-stop Results

• Expected: Use no_clock checks and targeted timing reports to correlate expected register groups with clock propagation through logical arcs. • Investigate: A primary clock is reported, yet a gated branch or generated domain never reaches its registers. • Stop before floorplanning when required logic or timing coverage is missing or unexplained. Repair clock/gating/generated-clock intent or netlist connectivity, then compare affected register groups.

Common Mistake

Do not assume the check passed just because ICC2 continued: A primary clock is reported, yet a gated branch or generated domain never reaches its registers. Fix or narrowly justify the named objects, then rerun the same command.

What The Interviewer Is Testing

Be ready to explain why this matters before floorplanning: A primary clock is reported, yet a gated branch or generated domain never reaches its registers.

Follow-up Question & Model Response

Model response: “I would save the report, inspect one affected object in the correct block and scenario, and make or request this correction: Repair clock/gating/generated-clock intent or netlist connectivity, then compare affected register groups. Then I would reopen the clean checkpoint and rerun the same evidence.”

Practical Example

Symptom: A primary clock is reported, yet a gated branch or generated domain never reaches its registers. Corrective path: Repair clock/gating/generated-clock intent or netlist connectivity, then compare affected register groups.

Original guide diagramHow do you prove clocks reach sequential clock pins?
How do you prove clocks reach sequential clock pins?, illustrating the physical design concept.