Level 2 · Construction & Debugging

Intermediate PnR Interview Questions

Learn pre-floorplan sanity checks, structural netlist integrity, SDC application, clock definitions, and floorplanning tradeoffs.

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Learn pre-floorplan sanity checks, structural netlist integrity, SDC application, clock definitions, and floorplanning tradeoffs.

  1. 09 Why are input and output delays needed, and what do min and max mean?Intermediate · Input and output delays describe timing outside the block boundary relative to a reference clock. Maximum and minimum values expose the late and early interface behavior needed for setup and hold analysis.
  2. 10 What clock information must be available before physical design?Intermediate · The handoff must identify real clock sources, generated-clock relationships, waveforms, and the timing assumptions for each operating mode. Clock-tree synthesis later implements distribution; it does not invent the functional clock specification.
  3. 11 What are TLUPlus and RC technology files, and why is a layer map needed?Intermediate · RC technology models translate interconnect geometry into resistance and capacitance. TLUPlus is a layer-specific parasitic model used by ICC2 native extraction; layer mapping aligns the extraction model's layer names with the implementation technology.
  4. 12 How is an RC technology file different from SPEF?Intermediate · An RC technology file is a reusable extraction model for a process; SPEF records extracted parasitic networks for a particular design. One describes how to calculate parasitics, and the other carries design-specific results.
  5. 13 What are PVT corners, modes, and MMMC scenarios?Intermediate · A mode describes how the design operates; a corner describes analysis conditions; an ICC2 scenario combines one mode and one corner. MMMC checks the design across multiple modes and corners instead of trusting one favorable case.
  6. 14 What should an initial floorplan input contain?Intermediate · An initial floorplan defines the physical envelope and key constraints within which placement and routing will operate. It can be supplied as DEF or scripts, or generated during the design-planning stage.
  7. 15 What files and information are required for SRAMs and other hard macros?Intermediate · A hard macro needs compatible logical/timing and physical information, together with its interface and integration requirements. A black box in the netlist is not a complete macro handoff.
  8. 16 What does UPF contain, and why is it separate from the netlist?Intermediate · UPF describes power intent: which logic belongs to power domains, how supplies and states are modeled, and what protection or state-preservation strategies are required. Logical connectivity alone cannot fully express power-state behavior.
  9. 17 What scan and DFT information is needed for physical design?Intermediate · Physical design needs the scan connectivity and allowed reordering constraints when it optimizes scan chains. A scan-inserted netlist describes connections; SCANDEF supplies scan-chain structure and constraints used by the physical optimization flow.
  10. 18 Are VCD or SAIF files mandatory inputs to place and route?Intermediate · Switching-activity files are conditional inputs. They improve activity-dependent power estimation and optimization, but are not universally required just to import and place a design.
  11. 19 How do you check consistency across all input files?Intermediate · Validate relationships between files, not just each file independently. Names, units, revisions, physical technology, library models, and operating assumptions must describe the same intended design.
  12. 20 How do you debug unresolved references or missing library cells?Intermediate · An unresolved reference means an instantiated design or cell cannot be bound to an appropriate definition. Debug the intended reference and library setup before altering the circuit to make the error disappear.
  13. 21 How do you find missing constraints and unsafe timing exceptions?Intermediate · Audit timing coverage and the meaning of exceptions in every required scenario. A clean slack summary can hide paths that were never checked or were removed from analysis by an overly broad exception.
  14. 22 In what order should inputs be loaded into ICC2?Intermediate · Load inputs in dependency order: establish the library and technology context, read and resolve the design, then apply compatible physical, power, and timing setup before validating and saving the initial state. The exact script follows the approved flow.
  15. 23 Which files are inputs, outputs, or conditional restart data?Intermediate · A file's role depends on the stage. A routed DEF or extracted parasitic file can be an output of one run and an input to a later analysis or restart; the extension alone does not define the flow.
  16. 24 The design loads and timing looks clean. Why can the inputs still be wrong?Intermediate · Successful import proves that the tool accepted data; clean timing proves only that the analyzed constraints passed. Neither proves that the files represent the intended chip or that all required cases were analyzed.
  17. 25 What is a strong final input-readiness checklist for physical design?Intermediate · A strong input-readiness review asks whether the next implementation stage can start reproducibly with complete, consistent intent. It records evidence and ownership for unresolved issues rather than stopping at a file checklist.
  18. 29 What do routing-track pitch and offset mean?Intermediate · Track pitch sets the distance between candidate routing centerlines. Track offset sets where the first centerline begins relative to the coordinate origin used by the track definition. Both are needed to locate a track.
  19. 30 What are a placement site, a standard-cell row, and cell height?Intermediate · A placement site is a reusable unit of legal placement geometry. A row arranges sites across the floorplan, and a standard cell occupies a compatible number of sites while respecting row height, orientation, and library rules.
  20. 31 How do manufacturing, placement, routing, and FinFET grids differ?Intermediate · These grids constrain different things. The manufacturing grid quantizes allowed geometry coordinates; placement sites constrain legal cell placement; routing tracks suggest wire centerlines; the FinFET placement grid constrains relevant cell and boundary alignment.
  21. 32 What are fin pitch, gate pitch, and contacted gate pitch in a FinFET technology?Intermediate · Fin pitch measures the center-to-center spacing between neighboring fins. Gate pitch measures the repeat spacing between neighboring gates. Contacted gate pitch, often called CPP, describes a gate-repeat metric that includes the required contact arrangement.
  22. 33 Why is FinFET transistor width quantized by fin count?Intermediate · In a conventional FinFET device family, adding parallel fins increases effective channel width in discrete increments. The designer cannot choose an arbitrary continuous width in the same way as a simple planar-width model might suggest.
  23. 34 How do you inspect and debug the FinFET placement grid in ICC2?Intermediate · Report the actual FinFET grid and run its dedicated check before changing geometry. ICC2's grid contains x/y spacing and offsets that guide placement of cells containing FinFET devices and can constrain relevant boundaries.
  24. 35 How can a placement be legal on one grid but fail another grid or pin access?Intermediate · Legality is the intersection of applicable rules, not a single snapped coordinate. A cell or macro can satisfy site placement while failing a FinFET boundary rule, or satisfy both but leave no legal routing access to a pin.
  25. 61 What command order preserves the meaning of failures?Intermediate · Establish identity and libraries, link, check structure/unbound objects, validate and apply SDC, inspect clocks/scenarios/exceptions, then run timing-health checks.
  26. 62 How do you make a sanity script version-conscious?Intermediate · Use get_design_checks to confirm available check bundles and man to confirm syntax in the installed release.
  27. 63 What does dp_pre_floorplan actually prove?Intermediate · It checks technology-file information, layer directions, and the presence of horizontal and vertical layers; it is only one readiness component.
  28. 64 How should ICC2 inventory be reconciled with synthesis reports?Intermediate · Compare like-for-like scope and object classes, accounting for known handoff transformations rather than demanding unexplained equality.
  29. 65 Why separate sequential, combinational, memory, and macro inventories?Intermediate · Class totals reveal missing domains or views that a single overall cell count can hide.
  30. 66 How do you distinguish an intentional open from broken connectivity?Intermediate · Trace the object to interface intent, tie-off policy, black-box boundary, and synthesis log; intention requires recorded ownership.
  31. 67 What evidence makes a black-box waiver defensible?Intermediate · The interface must have approved pin identity, timing boundary treatment, logical/physical views required for the next stage, revision, and owner.
  32. 68 How do you detect the wrong same-named library cell?Intermediate · Correlate reference-library order, cell view identity, PVT assignment, pin interface, and handoff version rather than trusting the instance reference text.
  33. 69 How do you find unit mismatches across SDC and libraries?Intermediate · Compare ICC2 user units with Liberty declarations and the values expected by the STA handoff; inspect representative periods, slews, delays, and loads.
  34. 70 Which constraints belong to modes, corners, scenarios, or the netlist?Intermediate · Functional intent commonly belongs to modes, operating-condition/parasitic intent to corners, combined analysis status to scenarios, and design-rule constraints can be netlist-specific.
  35. 71 Why inspect active analysis types in each scenario?Intermediate · A scenario can exist while setup, hold, or other required analysis is inactive.
  36. 72 What should be reviewed after read_sdc applies a file?Intermediate · Review errors, warnings, object-resolution messages, overridden constraints, current context, and resulting reports; parsing success is only the first gate.
  37. 73 How do renamed or optimised-away objects break constraints?Intermediate · Post-synthesis hierarchy and object names may differ from the intent source, causing selectors to resolve incorrectly or not at all.
  38. 74 How do you audit wildcard selectors safely?Intermediate · Measure the collection and inspect representative names before applying a constraint; scope should be explainable and stable.
  39. 75 How do you validate clock period and waveform?Intermediate · Compare reported period and edge waveform with the interface specification for each mode, including non-50-percent duty cycles when relevant.
  40. 76 How do you debug a generated clock's source and master?Intermediate · The reported master, source object, target pin, divide/multiply factor, phase, and edge mapping must match real logic connectivity.
  41. 77 How do you prove clocks reach sequential clock pins?Intermediate · Use no_clock checks and targeted timing reports to correlate expected register groups with clock propagation through logical arcs.
  42. 78 What does multiple clocks at one register clock pin mean?Intermediate · It can be intentional mode multiplexing or a missing exclusivity/case relationship; the report requires mode-aware interpretation.
  43. 79 How do you audit clock groups and inter-clock relationships?Intermediate · Every asynchronous, exclusive, or related declaration changes which crossings are analysed, so membership and mode scope must be reviewed.
  44. 80 Why are clocks normally ideal before floorplanning?Intermediate · There is no implemented clock tree, so built-tree skew and route latency do not exist; only justified early assumptions belong in the model.
  45. 81 How do source and estimated network latency differ pre-floorplan?Intermediate · Source latency models delay before the design clock source; estimated network latency is a methodology assumption inside the design and must not be confused with measured CTS latency.
  46. 82 How should pre-floorplan clock uncertainty be reviewed?Intermediate · Separate jitter, modelling margin, and setup/hold uncertainty according to methodology; ensure it is not duplicated by other margins.
  47. 83 Why check clock transition before CTS?Intermediate · An explicit pre-CTS transition can be a modelling assumption for cell delay; it is not a measured routed-clock slew.
  48. 84 How do you audit input-delay min and max completeness?Intermediate · For each timed input, confirm reference clock, edge, rise/fall scope, and both early and late interface intent where required.
  49. 85 Why should input delay not be applied indiscriminately to clock ports?Intermediate · A clock port defines timing reference behaviour and is not ordinary launched data; bulk get_ports * selectors can impose nonsensical data delay.
  50. 86 How do you audit output-delay constraints?Intermediate · Verify receiving reference clock, edges, sign convention, min/max values, and whether the external requirement matches the interface specification.
  51. 87 When should a driving cell be used instead of set_input_transition?Intermediate · A driving cell models a library-based source response, while explicit transition provides a direct slew assumption; methodology should choose and avoid conflicting intent.
  52. 88 How do you verify output loads?Intermediate · Correlate load values with receiver and package assumptions, units, modes, and min/max analysis needs.
  53. 89 How do you audit false paths without masking real timing?Intermediate · Inspect exact from/through/to membership, mode scope, precedence, affected path count, and functional reason.
  54. 90 How do you audit multicycle setup and hold intent?Intermediate · Confirm the functional cycle relationship, start/end clocks, edge convention, and paired hold behaviour instead of applying a number mechanically.
  55. 141 How do you select target utilisation without using a universal percentage?Intermediate · Start from counted area, macro dominance, expected growth, physical-only cells, clock and hold buffering, spare strategy, routing access, PG reservation, voltage areas, and local density risk. Then test alternatives.
  56. 142 Why does a macro-dominated block need different area reasoning?Intermediate · Macro dimensions and channels often determine the outline before standard-cell area does. Dividing total area by one utilisation target can hide geometric infeasibility.
  57. 143 How do you test floorplan sensitivity to cell-area growth?Intermediate · Recalculate required placeable area with the larger counted cell area, rebuild or resize the candidate, and compare rows, congestion, timing, and PG capacity using the same method.
  58. 144 How do you compare equal-area floorplans with different aspect ratios?Intermediate · Keep area, constraints, macro set, PG assumptions, and evaluation settings constant; compare path length, row continuity, channel capacity, pin affinity, congestion, and change risk.
  59. 145 How do you calculate and round a core and die consistently?Intermediate · Calculate ideal core dimensions, snap them to legal grids or row/site multiples, recompute actual area and utilisation, then add asymmetric offsets.
  60. 146 How do you debug rows created with the wrong site?Intermediate · Compare row site names, library cell site compatibility, row height/width, orientation, voltage area, and the intended row pattern.
  61. 147 How do you decide whether a row fragment is useful?Intermediate · Measure its legal length, site alignment, voltage-area ownership, nearby keepouts, and whether intended cells plus required spacing can fit.
  62. 148 How do you diagnose a row rail-orientation problem?Intermediate · Compare row orientation and alternation with the standard-cell library’s legal orientations and power-rail convention.
  63. 149 How do connectivity and timing guide macro placement?Intermediate · Use flylines, bus width, path criticality, producer-consumer order, I/O affinity, clock/reset sources, and hierarchy to propose macro regions.
  64. 150 When should macros be edge-biased versus placed internally?Intermediate · Edge placement can simplify external access and preserve central rows; internal placement can shorten central dataflow but creates more channel and blockage interactions.
  65. 151 How do rotation and mirroring change macro dataflow?Intermediate · They move pin walls relative to neighbours and may change supply-pin alignment. The macro outline can remain legal while routes become much longer.
  66. 152 How do you verify macro and block-grid alignment?Intermediate · Check macro origin, boundary, orientation, alignment point, and applicable block or FinFET grid. Movement, rotation, mirroring, and snapping are separate operations.
  67. 153 How do you estimate whether a macro channel is wide enough?Intermediate · Start with usable routing layers and track pitches, subtract PG straps, blockages, via keepouts, shielding, and edge rules, then compare remaining directional capacity with signal and pin demand.
  68. 154 Why are notches and narrow channels risky?Intermediate · They concentrate routes and pins, fragment rows, complicate PG continuity, and can create dead space that neither cells nor wires use well.
  69. 155 How do you choose a macro keepout type?Intermediate · Choose by which objects must be excluded and for which stage: hard for broad placement exclusion, soft when later optimisation cells may be allowed, hard_macro to exclude hard macros, and routing_blockage when routing shapes must be kept away.
  70. 156 How do hard, soft, partial, and macro-only placement blockages differ?Intermediate · A hard blockage excludes placement, a soft blockage can permit selected later optimisation use, a partial blockage limits occupancy, and a macro-only restriction targets hard macros. Exact behaviour must follow the installed release and methodology.
  71. 157 How do you plan boundary cells around rows and voltage areas?Intermediate · Select library-approved left, right, top, bottom, inside-corner, and outside-corner cells for the actual row and voltage-area geometry, then report rules before insertion.
  72. 158 How should I/O guides and place_io be used?Intermediate · I/O guides reserve legal regions for I/O driver cells, while constraints describe package, protocol, power, and matching intent. place_io applies those rules to the intended guides.
  73. 159 How should hierarchical block pins be placed?Intermediate · Place block pins on legal sides, layers, tracks, and offsets according to top-level dataflow, routing corridors, bundles, and feedthrough intent.
  74. 160 How do buses and differential pairs change pin planning?Intermediate · Buses need deliberate ordering and corridor width; differential pairs need paired routing opportunity and consistent constraints. Both can be harmed by corner crowding or arbitrary spreading.
  75. 161 When is a feedthrough better than routing around a block?Intermediate · A feedthrough is better when the top-level distance and timing benefit exceeds the block’s pin, route, voltage-area, buffering, and ECO cost.
  76. 162 How do you interpret feedthrough reports?Intermediate · Classify original, created, buffered, reused, redundant, unused, pure, and mixed feedthroughs; then inspect the nets whose classification conflicts with intent.
  77. 163 How do you create a repeatable early-congestion estimate?Intermediate · Use the same floorplan version, coarse placement, scenarios, layer availability, PG/blockage assumptions, global-route mode, and report settings for every alternative.
  78. 164 What is the correct order for fixing an early congestion hot spot?Intermediate · Confirm data and constraints, locate demand and capacity, identify the physical cause, make the smallest causal change, then rerun the same measurement.
  79. 165 How do pitch, offset, direction, and width define routing tracks?Intermediate · Pitch controls repetition, offset sets the first coordinate, direction selects X or Y track lines, and width can reserve a wire width. Technology rules decide legality.
  80. 166 How do you debug an off-track or blocked pin?Intermediate · Report its layer, side, and offset; compare with the track pattern, preferred direction, blockages, PG shapes, spacing rules, and neighbouring pins.
  81. 167 How do you test a power-grid reservation against signal-routing capacity?Intermediate · Overlay proposed ring, strap, rail, and via corridors on the same channel and congestion model used for signals, then compare remaining tracks and pin approaches.
  82. 168 How do you plan a usable voltage area?Intermediate · Shape and size it for assigned cells, expected growth, legal rows, boundary cells, isolation/level-shifter/retention zones, switch corridors, macro compatibility, and supply access.
  83. 169 How do you compare timing between two floorplan alternatives?Intermediate · Use the same netlist, SDC, scenarios, libraries, pre-CTS clock assumptions, coarse placement, and estimation method. Compare the same named paths and physical distances.
  84. 170 What should a reproducible floorplan evidence package contain?Intermediate · Include input and tool provenance, area assumptions, boundaries, rows/sites/tracks, macro and pin constraints, voltage areas, keepouts/blockages, reports, check results, images, waivers, and a write-out that reloads cleanly.