How does the effective-capacitance (k-factor) model correct for what Elmore delay gets wrong, and why must k be computed iteratively?
From PDVerse PnR Interview Handbook · pdVerse Mentor Guide
Short Answer
Given driver resistance R_d, wire resistance R_w, and loads C1/C2, wire delay is D_w = R_d(C1+C2) + R_wC2. If R_d >> R_w, driver delay is accurately a function of total load (C1+C2). If R_w is comparable to or exceeds R_d, driver delay decreases and part of C2 is shielded, so delay is characterized as a function of (C1 + k*C2), where k (the effective capacitance factor) ranges 0 to 1. Because k itself depends on driver resistance -- which depends on the delay being computed -- it has to be computed iteratively, independent of any specific driver model, rather than solved in one closed-form step.
Technical Explanation
- Given driver resistance R_d, wire resistance R_w, and loads C1/C2: wire delay D_w = R_d(C1+C2) + R_wC2.
- If R_d >> R_w, driver delay is accurately a function of the TOTAL load (C1+C2) -- Elmore-style summation works fine here.
- If R_w is comparable to or exceeds R_d, driver delay decreases and part of C2 is effectively shielded from the driver -- delay is then characterized as a function of (C1 + k*C2), where k ranges 0 to 1.
- k (the effective capacitance / k-factor) depends on driver resistance -- but driver resistance itself depends on the delay being computed, creating a circular dependency that has to be resolved ITERATIVELY, not in one closed-form calculation.
- This iterative computation is done independent of any specific driver model -- it's a general correction mechanism, not tied to one particular cell's characterization.
Formula Or Decision Rule
D_w = R_d(C1+C2) + R_wC2 in general; when R_w is significant, effective load becomes (C1 + k*C2) with 0 <= k <= 1, computed iteratively since k depends on R_d which depends on the delay itself.
What To Check
- Warning sign: delay calculation for a net with significant wire resistance relative to driver resistance converges slowly or shows instability during extraction/timing.
- Inspect: confirm the delay-calc engine is genuinely iterating to solve for k rather than using a single-pass approximation on a net where R_w is significant.
- Correct: this is expected behavior for resistance-significant nets -- the iteration is inherent to getting an accurate k-factor, not a sign of a problem to eliminate.
Command Checks & Actions
report_net -parasitics [get_nets ...]Verify exact command name against the ICC2 Implementation User Guide’s parasitics/timing chapter -- reports the extracted R_w/C values feeding the iterative k-factor calculation for a given net, versus an estimated value.
Healthy, Suspicious & Hard-stop Results
- Expected: nets with wire resistance comparable to driver resistance show delay-calc results consistent with iterative k-factor correction, not a naive full-load Elmore assumption.
- Investigate: delay-calc results for a resistance-significant net look identical to what a naive full-load (C1+C2) Elmore calculation would predict -- worth confirming the k-factor correction is actually being applied.
- Stop: a hand-verification of a critical net's delay assumes k=1 (no shielding) on a net where wire resistance is clearly significant relative to driver resistance -- that assumption discards the entire point of the k-factor correction.
Common Mistake
The Trap: Treating k-factor computation as a one-shot closed-form calculation -- it's inherently iterative because k depends on driver resistance, which depends on the very delay the k-factor is being computed to help calculate.
What The Interviewer Is Testing
Whether you understand WHY k-factor computation must be iterative (the circular dependency between k and driver resistance), not just that k exists as a correction between 0 and 1.
Practical Example
Debug Scenario: A net with high wire resistance relative to its driver shows a delay noticeably lower than a naive (C1+C2)-based Elmore estimate would predict -- consistent with effective capacitance correctly modeling C2 as partially shielded (k < 1) rather than fully counted.
Physical Design & Planning Handbook
Master ASIC Physical Design Planning & Floorplanning
Dive into 14 comprehensive chapters covering netlist sanity, FinFET grids, macro placement, power grids, CTS, and timing budgeting.
Continue practising