What does the logical effort delay formula actually decompose gate delay into, and what does g=1 for an inverter specifically mean?

Short Answer

Total CMOS gate delay: d = p + f (p = parasitic/intrinsic delay, f = effort/extrinsic delay), in units of tau (process-characterized delay through the smallest inverter). f = g*h (g = logical effort, h = electrical effort/gain = Cl/Ci). Logical effort g = T_gate / T_inverter -- the cell's ability to produce output current based on topology, independent of transistor size. A typical inverter (2 PMOS + 1 NMOS transistor units, equal rise/fall) has T=3, giving g=1 -- inverters are the BASELINE; more complex gates are slower (g>1) purely from their topology, before size is even considered.

Technical Explanation

• Total CMOS gate delay: d = p + f, where p = parasitic/intrinsic delay and f = effort/extrinsic delay -- both measured in units of tau, a process-characterized reference delay (the delay through the smallest possible inverter).
• f = g * h, where g = logical effort (topology-dependent) and h = electrical effort/gain = Cl/Ci (output load capacitance over input capacitance).
• Logical effort g = T_gate / T_inverter -- literally the ratio of a cell's total transistor-width units to an inverter's, capturing the cell's ability to produce output current based purely on TOPOLOGY, independent of how large you actually build it.
• A typical inverter (2 PMOS-width units + 1 NMOS-width unit, sized for equal rise/fall) has T=3, giving g=1 -- inverters are the explicit BASELINE for this whole system.
• A more complex gate (e.g. a multi-input NAND or NOR) inherently has g>1 -- it's slower than an inverter purely from its logical structure, BEFORE you even consider how large you build it.
• Total delay: d = g*h + p -- both g and p are independent of transistor SIZE; h is the term that relates directly to size (via Ci in the denominator).

Formula Or Decision Rule

d = p + f = p + g*h, where g = T_gate/T_inverter (topology-dependent, g=1 for an inverter), h = Cl/Ci (size-and-load-dependent), all in units of tau.

What To Check

• Warning sign: a hand estimate of gate delay using only load capacitance (ignoring logical effort) doesn't match the tool's actual reported delay for a complex gate like a multi-input NAND/NOR or XOR.
• Inspect: account for the gate's logical effort g (its topology-driven baseline slowness relative to an inverter) in addition to its electrical effort h.
• Correct: for a quick sanity estimate of complex-gate delay, multiply g (from the gate's known topology) by h (load/input capacitance ratio) rather than assuming h alone determines delay.

Healthy, Suspicious & Hard-stop Results

• Expected: hand estimates of relative gate delay (accounting for both logical effort g and electrical effort h) roughly track the tool's actual reported delays for different gate topologies.
• Investigate: a hand estimate based on load alone (ignoring g) significantly underestimates delay for a complex gate -- expected, since logical effort's topology-driven contribution was left out of the estimate.
• Stop: a design decision about gate topology choice (e.g. NAND vs NOR vs a complex AOI gate) is made purely on load capacitance without any consideration of each topology's different logical effort.

What The Interviewer Is Testing

Whether you can state the actual formula (d=p+gh) and correctly distinguish g (topology, size-independent) from h (load ratio, size-dependent), not just recite "logical effort matters for delay."