Setup vs Hold Time, Slack, Skew, and Jitter: Complete STA Interview Guide
Static Timing Analysis (STA) interviews test fundamental silicon timing behavior: how sequential registers reliably capture and hold digital state across process, voltage, temperature variations, and clock distribution networks. This guide breaks down the core equations, physical mechanisms, and interview traps.
1. Setup Check Anatomy & Equations
In digital synchronous ASIC design, a setup check guarantees that combinational logic outputs settle to a valid, stable voltage level before the sequential capture flip-flop samples the input pin. If data arrives too late, the internal master latch in the flip-flop can enter a metastable state, producing undefined logic values.
The standard setup check compares the maximum data arrival time against the minimum required capture time over a full clock cycle:
Setup Slack = (T_capture + T_period - T_uncertainty - T_setup) - (T_launch + T_clk2q_max + T_comb_max)
In Synopsys PrimeTime or Cadence Tempus reports, data arrival represents the late path (slowest corner, highest RC delay, lowest supply voltage), whereas the clock required time is evaluated with early path derates and clock uncertainty deducted.
→ Practice Full Q&A: Setup check anatomy and setup margin equations2. Hold Check Mechanics & Min-Delay Rules
A hold check ensures that newly launched data does not race through fast combinational paths and corrupt data currently being latched by the capture register during the active clock transition. Unlike setup, hold verification is a same-edge (or zero-cycle) comparison.
Because the launch and capture actions are initiated by the same logical clock transition, the clock period T_period does not appear in the hold timing check:
Hold Slack = (T_launch + T_clk2q_min + T_comb_min) - (T_capture + T_hold + T_uncertainty)
A chip with setup violations can frequently operate at reduced clock frequencies in the lab. A chip with a single uncorrected hold violation is functionally dead silicon because slowing the clock does not increase hold margin.
3. Slack Calculation & Signoff Margins
Slack is the numerical difference between the required arrival time and the actual data arrival time. Positive slack indicates timing compliance; negative slack represents a timing violation that must be closed prior to tapeout.
| Check Type | Constraint Goal | Late vs Early Corner | Slack Formula |
|---|---|---|---|
| Setup Check | Max delay constraint | Data: Late corner / Clock: Early corner | Required Time - Arrival Time |
| Hold Check | Min delay constraint | Data: Early corner / Clock: Late corner | Arrival Time - Required Time |
| Recovery Check | Async pin de-assertion setup | Reset de-assertion vs active clock edge | Required Time - Arrival Time |
| Removal Check | Async pin de-assertion hold | Reset de-assertion stability window | Arrival Time - Required Time |
4. Positive vs Negative Clock Skew
Clock skew is the spatial variation in arrival times of an active clock edge across two distinct sequential elements: Skew = T_capture_clock - T_launch_clock.
- Positive Clock Skew (Capture Later than Launch): Increases the allowable combinational logic delay for setup checks (
+T_skewadded to setup budget). However, it directly degrades hold margin because capture happens later while data begins propagating immediately. - Negative Clock Skew (Capture Earlier than Launch): Reduces allowable combinational logic delay for setup checks, making high-speed timing closure harder, but naturally protects against hold race conditions.
- Useful Skew: In modern CTS and physical synthesis (e.g., PrimeTime / Innovus CCD - Concurrent Clock and Data), designers deliberately introduce controlled positive skew to steal timing margin from fast paths and fix setup violations on critical paths.
5. Clock Jitter & SDC Uncertainty Modeling
While clock skew represents spatial variation across physical locations, clock jitter represents temporal variations in clock edge placement over successive cycles at the same node. Jitter is caused by PLL phase noise, power supply ripple, and thermal variations.
In SDC constraints, clock uncertainty is modeled using set_clock_uncertainty, which aggregates multiple pessimism sources:
set_clock_uncertainty -setup 0.120 [get_clocks SYS_CLK]
# Hold uncertainty models clock skew jitter and duty cycle distortion
set_clock_uncertainty -hold 0.050 [get_clocks SYS_CLK]
6. Fixing Setup vs Hold in Implementation
During physical synthesis, CTS, routing, and post-route ECO loops, timing engineers apply distinct strategies to close setup and hold violations without creating secondary timing regressions:
- Fixing Setup Violations: Upsize driving standard cells, swap high-Vt (HVT) cells to low-Vt (LVT/ULVT), restructure logic hierarchies, insert pipeline registers, reduce wire parasitics via wider metal layers, or apply useful skew.
- Fixing Hold Violations: Insert delay buffers (or lockup latches across clock domains) on fast data paths, downsize driving gates, swap ULVT/LVT cells to SVT/HVT cells to increase cell propagation delay without increasing area or power excessively.
7. High-Frequency Interview FAQs
What is the fundamental difference between a setup check and a hold check?
A setup check is a max-delay constraint ensuring data arrives before the next active capture clock edge by at least Tsetup. A hold check is a min-delay constraint ensuring newly launched data does not overwrite currently sampled data before Thold.
Why can hold violations not be fixed by reducing clock frequency?
Hold checks occur between the same clock edge (or edge 0 to edge 0). The clock period (Tclk) does not appear in the hold slack equation: Slack_hold = Arrival_min - (T_capture + Thold). Changing clock frequency has zero impact on hold margin.
How does positive clock skew affect setup and hold margins?
Positive skew (capture clock arrives later than launch clock) helps setup margin by providing more time for data propagation, but harms hold margin because data must remain stable longer.