What is a setup check, and what is setup time?
From PDVerse STA Mentor Guide · pdVerse Mentor Guide
Short Answer
A setup check verifies that data launched by one clock edge arrives at the capturing flipflop's D pin early enough — specifically, at least a setup time (Tsu) before the capturing edge; it is a max-delay check.
Example
In a worked setup example, data arrives at 870 ps while the required time is 930 ps, giving a setup slack of +60 ps, which passes.
Why It Matters
Setup checks are what determine the fastest clock frequency a design can run at — if data doesn't stabilize before the setup window on the capturing edge, the flop can capture the wrong value, so setup failures directly limit chip speed.
Equation
setup slack = required - arrivalMentor Note — Common Mistake
Thinking you can always fix a setup violation just by adding buffers — you actually need to reduce path delay or slow the clock, since setup is fundamentally a maxdelay problem tied to how much time the data had to travel.
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