BeginnerQuestion 81 of 95Source: IC Compiler II Implementation User Guide: Creating ETMs and ETM Cell Libraries

What is an extracted timing model, ETM, in plain terms?

From PDVerse STA Mentor Guide · pdVerse Mentor Guide

Short Answer

An extracted timing model, ETM, is a simplified stand-in for a block's timing behavior, built by summarizing how each input pin affects each output pin, without keeping any of the internal gates that produced that behavior. It captures the delays and internal setup/hold checks the top-level design needs at the block's boundary, in a much smaller file than the block's full netlist and library data would require. Using an ETM instead of the full block lets a top-level run treat a large, complex block like a single, fast-to-load timing element.

Technical Reference DiagramWhat is an extracted timing model, ETM, in plain terms?
A netlist with 8,000 internal gates on one side collapsing into a small ETM box with 24 boundary pins and their delay arcs on the other side

Technical Explanation

An ETM keeps boundary behavior and discards the internal gates that produced it.

  • Building an ETM means running timing analysis on the block itself, then recording, for every input-output pin pair, the delay and slew behavior an external tool needs, without keeping the internal cells.
  • Internal checks that matter outside, like a setup check at an internal flop whose clock and data both come from boundary pins, are preserved as boundary checks even though the flop is not part of the model.
  • Because an ETM has no internal gates, variation cannot be recalculated at the top level the way it could with a full netlist; ETM extraction carries POCV-relevant data through despite this.
  • A combinational path looping through the clock network inside the block, like a clock-gating cell, is a modeling challenge the flow handles with a dedicated internal check pin.
  • ETMs are especially useful for hard IP where the internal netlist may not be available to the top-level team, since the ETM only exposes boundary behavior.

Common Mistake

The Trap: assuming an ETM is just a faster way to load "the same information" as the full netlist.

  • An ETM only preserves the input-output relationships it was built to capture; an unanticipated effect, like a loop through a clock-gating cell, may not be represented correctly.
  • Treating an ETM result as equivalent to a full flat analysis without occasionally validating against the real netlist can let a gap go unnoticed until silicon.

Follow-up Question & Model Response

Since an ETM is built once from the block's own timing analysis, does it need to be rebuilt every time something inside the block changes?

Candidate Model Response: Yes, an ETM only reflects the block's behavior at the moment it was extracted, so any internal change affecting boundary delay requires rebuilding it before the top-level analysis can trust it again. Teams rebuild the ETM as part of the block's regular signoff, treating it as a deliverable alongside the netlist, so the top level always integrates with a matching version. A stale ETM is a realistic way for a clean-looking report to quietly analyze an outdated block.

Practical Example

A USB PHY macro with 8,000 internal cells reduces to an ETM exposing just 24 boundary pins and their delay relationships, cutting file size from hundreds of megabytes to a few hundred kilobytes. When the PHY team adjusts an internal clock-gating cell's placement, they rebuild and re-deliver the ETM before the next top-level run.

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