What is cell delay?
From PDVerse STA Mentor Guide · pdVerse Mentor Guide
Short Answer
Cell (gate) delay is the time from when an input of a logic cell crosses its switching threshold to when the output crosses its threshold — essentially the internal switching delay of that gate.
Example
In the worked path example, gate U1 contributes a cell delay of 48 ps (its A-to-Z arc) as part of the overall chain leading to a 299 ps total data arrival time.
Why It Matters
Cell delay is looked up as a function of the input's transition (slew) and the output's capacitive load, so it changes depending on how sharp the incoming signal edge is and how much the gate has to drive — this is exactly what a delay calculator computes for every arc in a path.
Mentor Note — Common Mistake
Treating cell delay as a fixed, constant number for a given gate — it actually varies with input slew and output load, so the same gate can have very different delay values depending on where it sits in the design.
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