What is a standard cell timing library (Liberty), and what does it contain?
From PDVerse STA Mentor Guide · pdVerse Mentor Guide
Short Answer
A standard-cell library holds the characterized timing (and power) data for every logic cell used in the design, and Liberty (.lib) is the structured, text-based format used to write that characterized data down.
Example
Inside a Liberty file you'll find timing arcs, delay and output-slew values as functions of input slew and output load, timing checks like setup, hold, recovery, removal, and pulse width, plus pin capacitances for every cell.
Why It Matters
Without this characterized data, the STA tool would have no idea how long a signal takes to pass through a given gate, or how much margin a flop's setup and hold checks require. The library is effectively the tool's dictionary of how every cell behaves electrically.
Command
report_lib -unit nsMentor Note — Common Mistake
Don't think of the library as just a list of cell names and functions. It's fundamentally a timing (and power) database, describing measured electrical behavior, not just logical behavior.
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