Walk through the fix_eco_timing flow for setup versus hold, and explain why the recommended ECO fixing order matters.
From PDVerse STA Mentor Guide · pdVerse Mentor Guide
Technical Explanation
fix_eco_timing -type setup fixes setup violations using cell sizing only, with no buffer insertion or clock-network changes by default, while fix_eco_timing -type hold uses both cell sizing and buffer insertion, and the overall ECO order matters because each fixing step can create or interact with violations the next step must respect.
Timing-path Reasoning
Setup fixing avoids adding delay (buffer insertion would only make setup worse), so it relies purely on resizing cells to speed up the critical path. Hold fixing, by contrast, needs to add delay in some cases to prevent early-arriving data from beating the clock, so it uses both cell sizing and buffer/delay-cell insertion (e.g., from a buffer_list of BUFX2, DLY1X2, DLY2X2). The recommended overall order in the ECO table is: (1) fix_eco_power for power recovery without introducing new violations, (2) fix_eco_drc to resolve DRC/noise/electromigration issues via buffer insertion or cell sizing, which may itself alter setup/hold as needed, (3) fix_eco_timing, where setup fixing honors DRC constraints and may alter hold, and hold fixing honors both setup and DRC, and finally (4) a second fix_eco_power pass for final leakage recovery that introduces no new timing/DRC violations and no layout changes. This order matters because each stage's fixes can shift the timing/DRC landscape the next stage must respect — fixing timing before DRC, for instance, risks having DRC fixes reintroduce timing violations.
Command
fix_eco_timing -type setup; fix_eco_timing -type hold -pba_mode exhaustive
-buffer_list {BUFX2 DLY1X2 DLY2X2}Switch-by-switch
-type setup selects setup-violation fixing (cell sizing only, no buffer insertion or clocknetwork changes by default). -type hold selects hold-violation fixing (uses both cell sizing
and buffer insertion). -pba_mode exhaustive selects the exhaustive path-based analysis
mode for the fixing pass. -buffer_list specifies the allowed buffer/delay cells (e.g., BUFX2,
DLY1X2, DLY2X2) available for insertion during hold fixing. -ignore_drc, -verbose, and estimate_unfixable_reasons are additional options controlling DRC interaction and
diagnostic output.Expected Result
Following the Table 66 order — power recovery, then DRC fixing, then setup fixing (honoring DRC), then hold fixing (honoring setup and DRC), then a final power recovery pass — converges the design to a state with minimized violations and no unintended new DRC/timing/leakage regressions.
Failure Symptoms
Running fixes out of order, e.g., timing before DRC or hold before setup, risks a DRC pass afterward re-perturbing the corrected timing, or a hold fix stage disregarding a setup constraint it should have honored, leading to iterative thrashing between violation types.
Root Cause
Interdependencies between power, DRC, setup, and hold fixes mean each stage's changes can affect the conditions the next stage assumes, so an order that respects those dependencies (power first with no side effects, DRC before timing, setup before hold, power recovery last) avoids repeated undoing of prior fixes.
Mentor Note — Debugging Procedure
If violations reappear after an ECO pass, check whether the fixing order deviated from the recommended sequence (power, DRC, setup, hold, power) and rerun in the correct order, using -verbose and -estimate_unfixable_reasons to diagnose any cells that could not be fixed. Setup fixing is sizing-only because adding delay would defeat the purpose, hold fixing needs both sizing and delay insertion, and the prescribed powerDRC-setup-hold-power order exists specifically to prevent later fixing stages from undoing earlier ones.
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