SRAM Periphery and Timing

The bitcell array of lesson 5 cannot do anything on its own. Every access needs circuits around it: a decoder to raise one wordline, precharge to prepare the bitlines, sense amplifiers to read a small signal, write drivers to force new data, and timing circuits to sequence all of these within one clock cycle. Together these are called the periphery.

This lesson goes through each periphery block and then puts them together in a read timing diagram. The sizing ideas of lesson 2 and the bitcell behaviour of lesson 4 are used throughout, and the timing parameters defined here become the Liberty arcs of lesson 9.

Reading time: about 9 minutes.

6.1 The sequence of a read

Let us follow one read in a synchronous SRAM, assuming the address and control inputs are captured on the rising edge of the clock.

1. The clock edge latches the address and starts the internal timing.
2. The row decoder selects one row and its driver raises that wordline. Precharge has already been switched off.
3. The selected cells discharge one bitline of each column. The column multiplexer passes the selected columns to the sense amplifiers.
4. When the differential is large enough, the timing circuit fires the sense-amplifier enable (SAE). The sense amplifiers resolve to full logic levels and the output latches drive Q.
5. The wordline is turned off and precharge restores the bitlines for the next cycle.

6.2 The row decoder and predecoding

Our 2048 x 64 macro with a mux of 4 has 512 rows, so the decoder must turn 9 row-address bits into one of 512 wordlines. A direct approach would give each row a 9-input AND gate. As lesson 2 showed, a gate with many series transistors has a high logical effort and is slow, and each address line would also drive 512 gate inputs.

The standard solution is predecoding. The 9 bits are split into three groups of 3. Each group drives a small 3-to-8 predecoder, producing 3 x 8 = 24 predecoded lines, of which exactly one in each group is high. Each row then needs only a 3-input gate that picks one line from each group, followed by the wordline driver.

Row address  A[10:2]   split into  {A[10:8]}, {A[7:5]}, {A[4:2]}
Predecode    3 x (3-to-8)          = 24 lines, one high per group
Final stage  512 x NAND3 + driver  = one wordline high
## Each predecoded line drives 512 / 8 = 64 final gates

The wordline driver at the end must charge a long wire loaded by the gates of every access transistor in the row – two per cell across 256 columns, or 512 gates in our case. This is exactly the problem solved by a tapered inverter chain in the logical-effort worked example of lesson 2. In most designs, the final decode is also gated by a clock-derived enable, so that the wordline is a pulse: it rises only after the address is stable and falls as soon as the read is complete.

6.3 Precharge and equalization

Each column has three PMOS transistors controlled by a precharge signal: one from VDD to BL, one from VDD to BLB, and one between BL and BLB. The first two pull both bitlines to VDD. The third, the equalizer, shorts the two together so that they end up at exactly the same voltage, even if the precharge devices are slightly mismatched. Precharge must be switched off before the wordline rises; otherwise, the precharge transistors would fight the bitcell and the differential would never develop.

6.4 The sense amplifier

The bitcell can only produce a small differential in a reasonable time, because its read current is small and the bitline capacitance is large. A sense amplifier converts that small differential into a full logic level. The most common type in modern SRAMs is the latch-type sense amplifier, shown in Fig. 6.1.

While SAE is low, the tail transistor MN3 is off and the isolation PMOS transistors are on, so the internal nodes S and SB follow the bitlines and acquire the same small differential. When SAE rises, the isolation transistors turn off and the tail turns on. The cross-coupled pair now forms a latch with strong positive feedback. The node that started slightly lower is pulled to ground and the other is pulled to VDD, typically within a few tens of picoseconds. Because the latch is isolated from the bitlines, it has only a small capacitance to drive, which makes it fast and also stops it from discharging the bitlines fully, saving energy.

The latch has one weakness. Random mismatch between its transistors gives it an input offset: a differential below which it may resolve the wrong way. The bitline differential at the moment SAE fires must exceed the offset with margin, at every corner and for the worst sense amplifier in the macro. Thus, sense-amplifier offset is a direct input to the timing of SAE.

6.5 The write driver

For a write, the write driver of each selected column pulls one bitline firmly to ground and holds the other at VDD, according to the data bit. It is built from large NMOS pull-down transistors, gated by the write enable and the column-select signal, because – as lesson 4 explained – the access transistor must overpower the bitcell's pull-up through the bitline. Many macros also support a bit-write mask, where a mask input per bit (or per byte) blocks the write driver for that bit, leaving the stored value unchanged.

6.6 Self-timing with a replica bitline

When should SAE fire? Too early, and the differential is smaller than the offset. Too late, and the access is slow and the bitlines waste energy by discharging further. The time to develop the differential depends on the bitcell read current, which varies strongly with process, voltage and temperature. A chain of logic gates used as a delay line varies differently, so it cannot track the bitcell.

The common solution is a replica bitline. An extra column, built from the same bitcells, is connected so that a small number k of its cells, hard-wired to store 0, turn on together when any wordline fires. The replica bitline has the same capacitance as a real bitline, so it discharges about k times faster. An inverter detects when it has fallen to about half the supply, and that edge generates SAE and also terminates the wordline pulse. Because the replica uses the same cells, its timing tracks the real bitline across corners.

## Assuming, bitline capacitance C_BL = 50 fF (512 cells plus wire)
## Assuming, bitcell read current I_cell = 20 uA
## Assuming, required differential dV = 100 mV (offset plus margin)
t_develop = C_BL x dV / I_cell
          = 50e-15 x 0.1 / 20e-6         = 250 ps

## Replica: same capacitance, k cells, must fall by about VDD/2
## Assuming, VDD = 1.0 V, so the replica must swing 0.5 V in 250 ps
k = (VDD / 2) / dV = 0.5 / 0.1           = 5 cells

6.7 Read and write timing

Figure 6.2 puts the read sequence of section 6.1 on a time axis.

From the outside, the macro is described by a few timing parameters, which a datasheet and the Liberty model (lesson 9) report:

• Access time (clock-to-Q) – from the clock edge to valid read data at the output.
• Cycle time – the minimum clock period, which must cover the access plus the wordline reset and precharge.
• Setup and hold on address, data, chip enable and write enable, relative to the clock edge. Because the address feeds a decoder before reaching any latch, address setup is often larger than a flip-flop's setup time.
• Minimum clock pulse widths high and low, since the internal self-timed sequence needs time in each phase.

A write follows the same pattern, except that the write drivers act on the bitlines before the wordline opens, and the self-timed circuit allows enough wordline pulse width for the cell to flip. In many macros the write cycle, not the read, sets the minimum cycle time.

6.8 Interview questions

Why is predecoding used in a row decoder? It replaces one large, slow gate per row with small predecoders shared by all rows and a low-fan-in final gate, reducing both delay and the load on the address lines.

Why are latch-type sense amplifiers isolated from the bitlines when they fire? To remove the large bitline capacitance from the regenerating nodes, which makes the latch fast and stops it from fully discharging the bitlines.

What sets the earliest time SAE may fire? The bitline differential must exceed the worst-case sense-amplifier offset plus margin, across all corners.

Why use a replica bitline instead of a delay chain? The replica is built from the same bitcells and capacitance, so it tracks the real bitline's slow-down or speed-up across process, voltage and temperature. A logic delay chain does not.