The 6T SRAM Bitcell

The six-transistor (6T) SRAM bitcell stores one bit in two cross-coupled inverters and connects it to the outside world through two access transistors. It is the most replicated circuit on most chips. A modern processor may contain hundreds of millions of these cells, so every decision about the cell – its transistor sizes, its layout, the rules it is drawn with – is multiplied by that count.

This lesson explains how the cell holds, reads and writes data, why reading and writing pull its sizing in opposite directions, and how stability is measured with the butterfly curve. The inverter concepts of lesson 2 – switching threshold, noise margin and relative strength – are used throughout.

Reading time: about 9 minutes.

4.1 The schematic

Let us consider Fig. 4.1. The two inverters are formed by pull-up PMOS transistors PU1 and PU2 and pull-down NMOS transistors PD1 and PD2. The output of each inverter drives the input of the other, so the pair has two stable states: Q = 1 and QB = 0, or Q = 0 and QB = 1. The access transistors PG1 and PG2 (pass gates) are NMOS devices whose gates connect to the wordline WL. When WL is high, PG1 connects Q to the bitline BL and PG2 connects QB to the complementary bitline BLB.

4.2 Hold

When WL is low, both access transistors are off and the cell is isolated from the bitlines. The cross-coupled inverters reinforce each other: if Q is 1, PD2 is on and holds QB at 0, and QB = 0 keeps PU1 on, which holds Q at 1. This positive feedback holds the value for as long as the supply is present. Thus, the SRAM is static – it needs no refresh, unlike the DRAM of lesson 7 – but it is also volatile, since the data is lost when the supply is removed. Lesson 10 discusses how low the supply can go before the data is lost.

4.3 Read

Before a read, both bitlines are precharged to VDD (lesson 6 shows the precharge circuit). Let us assume the cell stores Q = 0 and QB = 1. When WL rises:

• On the right side, QB and BLB are both at VDD, so PG2 carries no current and BLB stays high.
• On the left side, current flows from BL through PG1 and PD1 to ground. BL begins to fall.

The sense amplifier needs only a small difference between BL and BLB, typically on the order of a hundred millivolts, before it resolves the value. However, there is a hazard. While current flows, PG1 and PD1 form a voltage divider, and node Q rises above 0. If Q rises past the switching threshold of the right inverter, the right inverter flips, QB falls, and the cell overwrites itself. This is called a read upset or destructive read.

To prevent it, PD1 must be stronger than PG1, so that Q stays close to ground. The measure of this is the cell ratio (also called the beta ratio of the cell):

CR = (W/L)_PD / (W/L)_PG                           (4.1)

A larger cell ratio gives a lower read-disturb voltage on Q and a more stable read. Textbook analyses typically find that a cell ratio somewhat above 1 is needed, and practical cells often use a ratio between about 1.5 and 2.5, chosen from simulation including variation.

4.4 Write

Let us now write a 0 into a cell that holds Q = 1. The write driver pulls BL to 0 and holds BLB at VDD, and then WL rises. Node Q must be pulled down through PG1, while PU1 – which is on, because QB is 0 – tries to hold Q at VDD. The write succeeds only if PG1 overpowers PU1 and pulls Q below the switching threshold of the right inverter. Once that happens, QB rises, PU1 turns off, and the feedback completes the flip.

Thus, writability requires the pull-up to be weak relative to the access transistor. The measure is the pull-up ratio:

PR = (W/L)_PU / (W/L)_PG                           (4.2)

A smaller pull-up ratio makes the cell easier to write. Since the PMOS is already weaker per unit width than the NMOS, minimum-size pull-ups are common.

Notice the conflict. Reading safely wants the access transistor weak (relative to the pull-down). Writing reliably wants the access transistor strong (relative to the pull-up). The final sizing must satisfy both, at all corners and with random variation between neighbouring transistors. This is the central difficulty of bitcell design, and it grows as the supply voltage is reduced.

## Candidate A
W_PU = 1.0   W_PG = 1.5   W_PD = 3.0
CR = 3.0 / 1.5 = 2.0       PR = 1.0 / 1.5 = 0.67

## Candidate B: access transistor widened for faster read
W_PU = 1.0   W_PG = 2.5   W_PD = 3.0
CR = 3.0 / 2.5 = 1.2       PR = 1.0 / 2.5 = 0.40

4.5 Read stability and the butterfly curve

The static noise margin (SNM) is the most common measure of bitcell stability. It is the largest DC noise voltage that can be applied to the storage nodes without flipping the cell. It is found graphically. The transfer curve of one inverter (QB against Q) is plotted together with the transfer curve of the other inverter with its axes swapped (Q against QB). The two curves form a shape like a butterfly, with two lobes. The SNM is the side of the largest square that fits inside the smaller lobe. Let us consider Fig. 4.2.

Two values are usually quoted. The hold SNM is measured with WL low and is relatively large. The read SNM is measured with WL high and both bitlines at VDD, which is the worst case during a read. It is smaller, because the access transistor lifts the 0 node, which degrades each inverter's low output. In most bitcells, read SNM is the limiting stability metric, and lesson 7 shows how the 8T cell removes it by separating the read path.

Writability is measured differently, since a successful write must destroy the stable state. One common measure is the write margin: the highest bitline voltage (or, in other methods, the lowest wordline voltage) at which the cell still flips. Circuit techniques that improve the margins at low voltage, such as lowering the wordline slightly during a read or driving the bitline below ground during a write, are called read assist and write assist.

4.6 Why the bitcell uses push rules

A logic layout must obey the foundry's standard design rules. The bitcell is allowed to break them. Foundries provide bitcells drawn with push rules – spacings and widths tighter than the logic rules – because the bitcell is a single, fixed layout that the foundry can characterize exhaustively with dedicated test structures, optimize with special lithography treatment, and qualify on silicon.

The push rules apply only inside the array, which is identified by a marker layer, and only for the foundry's approved bitcell layout. Hence, memory designers almost never draw their own bitcell. They use the foundry cell as delivered and design the periphery around it. For a PD engineer, this explains two facts: the macro interior is not checked with the usual rules (the DRC deck treats the marked region specially), and the memory is delivered as a hard macro that must not be modified.

4.7 Interview questions

Why must the pull-down be stronger than the access transistor? During a read, the access and pull-down transistors form a divider on the 0 node. A strong pull-down keeps that node below the trip point of the other inverter and prevents a read upset.

Why must the pull-up be weaker than the access transistor? During a write, the access transistor must pull the 1 node low against the pull-up. A weak pull-up lets it reach the trip point and flip the cell.

What is the static noise margin, and why is read SNM smaller than hold SNM? It is the side of the largest square inside the smaller lobe of the butterfly curve. During a read, the access transistor lifts the 0 node, which shrinks the lobes.

What are push rules? Design rules tighter than the logic rules, allowed only inside the foundry's qualified bitcell, because that one layout is characterized and qualified exhaustively.