What is glitch power, and how do you reduce it?
From PDVerse Low-Power Physical Design Mentor Guide · pdVerse Mentor Guide
Short Answer
Glitch power is the energy burned by spurious transitions: when the inputs of a gate arrive at different times, its output can toggle several times before it settles. Each extra toggle charges and discharges real capacitance, so it costs as much as a useful one, and in deep arithmetic logic those wasted edges add up to a real share of the block power. You reduce it by balancing path delays, cutting logic depth with pipelining, and stopping datapaths from toggling when their result is not needed.
Technical Explanation
- Mechanism: an XOR whose two inputs both flip, 150 ps apart, pulses for 150 ps even though its final output matches where it started.
- Propagation: each glitch drives the next gate as if it were real data, so glitches multiply through deep, unbalanced cones with reconvergent paths.
- Filtering: a gate slower than the pulse width absorbs it, so short glitches often die early while wide ones travel through the whole cone.
- Where it hurts: adders, multipliers and other arithmetic datapaths, where long carry chains and uneven depths make glitches a large share of switching power.
- Path balancing and pipelining: equalize arrival times at XOR and adder inputs, or add registers to cut depth, so glitches stop at a flop boundary.
- Operand isolation: hold datapath inputs steady when the result is unused this cycle, so neither useful toggles nor glitches happen downstream.
- Measuring it: zero-delay RTL simulation shows no glitches at all; you need timing-annotated gate-level activity, captured at the corner you sign off, to see them.
Common Mistake
The Trap: Estimating datapath power from zero-delay RTL simulation activity and treating it as final.
- Zero-delay simulation has no glitches, so a multiplier can look far cheaper than it is, and the gap only appears at gate-level power signoff.
- By then the floorplan, grid and package budget assume the lower number, and fixing it means retiming or re-architecting a datapath late.
Follow-up Question & Model Response
"Does clock gating remove glitch power?"
Candidate Model Response: Only in the cycles where the clock is gated and the cone inputs stop changing. Gating stops the registers from loading, so the logic after them sees stable inputs and does not glitch. When the block is active, the cone glitches exactly as before, because glitches come from unequal path delays inside one cycle. For active-mode glitch power you still need balancing, pipelining or operand isolation. Clock gating and glitch reduction solve different parts of the same dynamic power budget, so real designs use both.
Practical Example
Design Scenario: (illustrative) A 16x16 multiplier in PD_DSP draws 9 mW with zero-delay RTL activity and 14 mW with timing-annotated gate-level activity; the 5 mW gap is glitching in the partial-product adder tree. Adding one pipeline stage halfway through the tree cuts the gate-level number to 10.5 mW, at a cost of 32 flops and one cycle of latency. Operand isolation on the multiplier inputs saves another 2 mW in modes where the product is ignored. The final block power of 8.5 mW is measured at gate level, so the number the package team sees now includes glitching.
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