IntermediateQuestion 50 of 60Source: Synopsys PrimeTime User Guide: ECO Flow (Power Recovery); Multivoltage Design Flow (UPF Commands)

What's the basic flow to get a signoff power number in PrimeTime?

From PDVerse Low-Power Physical Design Mentor Guide · pdVerse Mentor Guide

Short Answer

Enable PrimePower with set_app_var power_enable_analysis true (PT), load the routed netlist with parasitics, constraints and the UPF, read switching activity with read_saif (PT) or read_vcd (PT), then run update_power (PT) and report_power (PT). The number is only as good as the activity behind it, so use a simulation of a real use case, not assumed toggle rates. Report by group to see where the power goes.

Technical Reference DiagramWhat's the basic flow to get a signoff power number in PrimeTime?
Flow: mychip.v netlist, SPEF parasitics, SDC, mychip.upf and an activity file (SAIF or VCD) feed a PT box with power_enable_analysis (PT) set true, then update_power (PT), then report_power -groups (PT) showing register 42 mW and combinational 118 mW of a 180 mW total.

Technical Explanation

  • License and switch: power analysis needs a PrimePower license, and power_enable_analysis (PT) must be true before any power command.
  • Inputs: netlist, read_parasitics (PT) for wire capacitance, SDC for clocks, and for multivoltage designs the UPF with set_voltage (PT) values.
  • Activity: SAIF carries average toggle rates per net; VCD carries the full time trace, which you need for peak or cycle-level power.
  • Without activity: the tool relies on assumed toggle rates, fine for early estimates but not a signoff number.
  • Groups: report_power -groups {register combinational sequential} (PT) splits internal, switching and leakage power per group.
  • Clock pin power: with power_clock_network_include_register_clock_pin_power (PT) false, register clock-pin power is booked to the register, not the clock network.
  • What breaks: a SAIF whose hierarchy does not match the netlist annotates little, and most nets fall back to default activity.
# [PrimeTime]  pt_shell
set_app_var power_enable_analysis true
read_verilog mychip.v
link_design
read_parasitics mychip.spef
read_sdc mychip.sdc
load_upf mychip.upf
set_voltage 1.0 -object_list [get_supply_nets VDD1p0]
read_saif video_decode.saif
update_power
report_power -groups {register combinational sequential}

What To Check

  • Activity annotation covers most internal nets, not just primary inputs.
  • The activity file comes from a named, realistic use case, not a reset-only test.
  • Supply voltages match the power state you are reporting.
  • Leakage is reported at the corner your spec names, often hot for standby.

Command Checks & Actions

PrimeTime (pt_shell)set_app_var power_enable_analysis true

Enable PrimePower analysis in the session

PrimeTime (pt_shell)read_saif video_decode.saif

Annotate average switching activity from simulation

PrimeTime (pt_shell)update_power

Run the power calculation

PrimeTime (pt_shell)report_power -groups {register combinational sequential}

Report internal, switching and leakage power per group

Healthy, Suspicious & Hard-stop Results

  • Healthy (illustrative): The SAIF annotates 97% of nets and total power lands at 180 mW, within 10% of the architecture estimate.
  • Suspicious (illustrative): Only 40% of nets annotate: the rest run on default activity, so the total is part measurement, part guess.
  • Hard stop: The number comes from a reset-only SAIF: 60 mW describes an idle chip and cannot sign off the use case.

Common Mistake

The Trap: Signing off power from a SAIF captured during reset or an idle test bench.

  • The toggle rates describe a chip doing nothing, so dynamic power reads far too low and the package and IR budgets are built on it.

What The Interviewer Is Testing

  • Do you know the answer depends on activity more than on the netlist?
  • Can you explain SAIF versus VCD and when each is enough?

Follow-up Question & Model Response

"When do you need a VCD instead of a SAIF?"

Candidate Model Response: SAIF holds average toggle counts and state probabilities, which is enough for average power over a use case. When you need power per cycle, such as peak power at wake-up or a current profile for dynamic IR, you need the time information in a VCD. VCDs are large, so teams dump a short, targeted window around the event. The rest of the PT flow stays the same apart from the read command.

Practical Example

Design Scenario: (illustrative) MYCHIP video decode: read_saif video_decode.saif (PT) annotates 97% of nets. report_power -groups {register combinational sequential} (PT) shows 180 mW total, with 42 mW in registers and 118 mW combinational, and leakage at 35 mW of the total. An earlier run with a reset-only SAIF showed 60 mW; that number described an idle chip, not the use case the package was sized for.

Low-Power & UPF Handbook

Read the complete low-power guide library covering power domains, level shifters, isolation clamps, state retention, and UPF signoff verification.

Static Timing Analysis (STA) Handbook — ten chaptersSTA HandbookTen chapters on setup, hold, OCV, and PrimeTime signoff. →