How do level shifters affect timing, and what does PT check at a voltage crossing?

Short Answer

A level shifter is a real cell on the path, and its delay depends on both its input and output supply voltages. PT times it from two-rail libraries characterized at voltage pairs, and separately checks signal levels with check_timing -include signal_level (PT) to catch crossings that need a shifter but lack one. set_level_shifter_threshold (PT) sets how large a driver-load voltage difference counts as a mismatch.

Technical Explanation

• Delay: the input stage runs on the input rail and the output stage on the output rail, so delay moves when either voltage moves.
• Multirail scaling: PT scales two-rail LS cells on both voltages; put their libraries in their own define_scaling_lib_group (PT), apart from one-rail cells.
• Library count: scaling a two-rail LS over voltage and temperature on the grid needs at least eight libraries, against four for one-rail cells.
• Signal level check: check_timing -include signal_level (PT) compares driver output and load input levels and reports incompatible voltages as errors, weaker mismatches as warnings.
• Threshold: set_level_shifter_threshold -voltage 0.1 -percent 5 (PT) flags a difference over 0.1 V or over 5% of the driver voltage. Both default to zero.
• What breaks: a missing shifter is not a timing violation, so report_timing can pass while a 0.7 V high never fully switches a 1.0 V gate.

# [PrimeTime]  pt_shell
define_scaling_lib_group {ls_0p7_0p7.db ls_0p7_1p0.db ls_1p0_0p7.db ls_1p0_1p0.db}
set_voltage 0.7 -object_list [get_supply_nets VDD0p7]
set_voltage 1.0 -object_list [get_supply_nets VDD1p0]
set_level_shifter_threshold -voltage 0.1 -percent 5
check_timing -verbose -include signal_level
report_power_pin_info [get_cells U_SNS/LS_0]
report_timing -voltage -through U_SNS/LS_0/A

What To Check

• Every LS instance shows both rail voltages in report_power_pin_info (PT).
• The LS libraries bracket the real pair: 0.7 V in, 1.0 V out.
• The signal-level check reports zero errors once all shifters are in.
• LS delay in report_timing -voltage (PT) is plausible for that voltage pair.

Healthy, Suspicious & Hard-stop Results

• Healthy (illustrative): Signal-level check clean; LS_0 shows a 0.7 V input rail, a 1.0 V output rail and 180 ps delay for that pair.
• Suspicious (illustrative): LS_0 delay stays at 180 ps when PD_SENSE drops to 0.63 V: the cell may not be scaling on its input rail.
• Hard stop: The signal-level check reports a PD_SENSE driver at 0.7 V into a 1.0 V load with no shifter: a missing LS, whatever the slack says.

What The Interviewer Is Testing

• Do you know why LS delay depends on two voltages, not one?
• Do you keep the signal-level check separate from the timing check?

Follow-up Question & Model Response

"Why can a high-to-low crossing sometimes skip the level shifter?"

Candidate Model Response: A 1.0 V output driving a 0.9 V input often still meets the load input levels, so no functional shifter is needed. Whether you can skip it depends on the library input_voltage limits and your threshold setting. PT flags an incompatible voltage error if the driver output maximum exceeds the load input maximum. Low-to-high is different, because a weak high leaves the load partly on, so that direction needs a shifter.