How does PrimeTime use the UPF for timing?

Short Answer

PrimeTime reads the UPF with load_upf (PT), builds a virtual model of the power network and pushes each supply net voltage down to the PG pins of every leaf cell. You give the voltages with set_voltage (PT), and each cell is then timed at its own supply voltage. PT does not read the power state table directly, so your voltages must match the one PST state you mean to verify.

Technical Explanation

• Connectivity: UPF domains, supply nets and strategies tell PT which supply feeds each cell; PT uses the UPF but never modifies or writes it.
• Voltages: a single set_voltage (PT) value is the max-delay voltage; -min sets the min-delay voltage, which the PT guide says is typically the larger value.
• Precedence: UPF port supply settings beat set_voltage (PT), which beats design operating conditions, which beat the library voltage_map default.
• One state per run: each PST state you care about needs its own voltage set, as a separate run or scenario.
• Missing voltage: a supply without set_voltage (PT) falls back to operating conditions or library voltages, so a 0.9 V domain can be timed at 1.0 V.
• Relink drops UPF: loaded UPF is removed on relink, like SDC, so reload it after any link_design (PT).
• Check it: report_supply_net (PT), report_power_domain (PT) and report_power_pin_info (PT) show what each net and pin really got.

# [PrimeTime]  pt_shell
read_verilog mychip.v
link_design
load_upf mychip.upf
read_sdc mychip.sdc
set_voltage 1.0 -object_list [get_supply_nets VDD1p0]
set_voltage 0.81 -min 0.99 -object_list [get_supply_nets VDD0p9]
set_voltage 0.0 -object_list [get_supply_nets VSS]
report_supply_net
report_power_domain
check_timing -include supply_net_voltage

What To Check

• Every UPF supply net has a voltage that matches one PST state.
• PD_CPU cells show 0.81 V and 0.99 V in report_power_pin_info (PT), not 1.0 V.
• The UPF was loaded after the final link_design (PT).
• No unconnected PG pins in check_timing -include unconnected_pg_pins (PT).

Healthy, Suspicious & Hard-stop Results

• Healthy (illustrative): PD_CPU cells show 0.81/0.99 V and PD_MYCHIP cells 1.0 V, matching the PST state being signed off.
• Suspicious (illustrative): A few cells show the (*) exceptional connection mark in the pin report; check their PG connections before trusting their voltage.
• Hard stop: PD_CPU cells show 1.0 V: VDD0p9 never got a voltage, so every PD_CPU setup path was timed too fast.

What The Interviewer Is Testing

• Do you know PT picks voltages from set_voltage, not from the PST?
• Can you read -min correctly as the min-delay voltage?

Follow-up Question & Model Response

"How do you time PD_DSP, which runs at either 1.1 V or 0.9 V?"

Candidate Model Response: PT times one voltage per supply at a time, so each DVFS point is its own analysis. Run one scenario with the PD_DSP supply at 1.1 V and one at 0.9 V, each with its matching constraints and libraries. For paths that cross domains, simultaneous multivoltage analysis covers the supply combinations in one run. Either way the voltages must match real PST states, or you sign off a state the chip never enters.