How do you build a clock tree that crosses power domains?

Short Answer

A clock that enters a domain at a different voltage needs a level shifter like any other signal, but ICC2 does not insert level shifters on clock nets by default. You name the clock nets in mv.upf.auto_ls_clock_nets (ICC2) and allow shifting on ideal nets with mv.upf.allow_ls_on_ideal_networks (ICC2). Then you keep the shifted branch balanced, watch duty cycle, and make sure clock buffers feeding always-on logic stay on when their domain powers down.

Technical Explanation

• Clock level shifting: a low-to-high clock crossing needs a level shifter; ICC2 skips clock nets unless you list them in mv.upf.auto_ls_clock_nets (ICC2).
• Set that option to specific clock nets, or to "*" for every clock net that needs shifting.
• mv.upf.allow_ls_on_ideal_networks (ICC2) defaults to false; set it true so shifters go in while clocks are still ideal.
• Delay and duty cycle: a level shifter adds insertion delay on one branch and can distort rise and fall, so balance and check duty cycle.
• Always-on clock branches: clock buffers in a shutdown area that feed always-on logic must be dual-rail AO cells.
• Gate the clock of a domain before it powers down, so no edge hits registers while their rail collapses.
• A missing clock level shifter leaves a weak high level at the sink, causing duty-cycle errors or no clocking at all.

# [UPF]  design.upf
set_level_shifter ls_cop_in -domain PD_COP -applies_to inputs -rule low_to_high -location self
# [ICC2]  icc2_shell
set_app_options -name mv.upf.auto_ls_clock_nets -value {CLK_TOP}
set_app_options -name mv.upf.allow_ls_on_ideal_networks -value true
create_mv_cells -level_shifter
check_mv_design -level_shifter
report_mv_path -level_shifter -net CLK_TOP

What To Check

• Every clock net that crosses a voltage boundary is listed in mv.upf.auto_ls_clock_nets (ICC2) or has an instantiated level shifter.
• Level shifters on clock paths are sized for balanced rise and fall and included in the skew targets.
• Clock buffers in shutdown areas that drive always-on sinks are dual-rail.
• check_mv_design -level_shifter (ICC2) reports no voltage-shifting violations on clock nets.

Healthy, Suspicious & Hard-stop Results

• Healthy (illustrative): CLK_TOP has one level shifter at the PD_COP edge, skew across both domains is 25 ps against a 40 ps target, and duty cycle stays within 48 to 52%.
• Suspicious (illustrative): Level shifter in place but it adds 90 ps on the PD_COP branch, leaving CTS little room to balance it.
• Hard stop: check_mv_design (ICC2) reports a 0.9 V to 1.0 V shifting violation on CLK_TOP because the clock net was never listed.

What The Interviewer Is Testing

• Knows the clock-net level shifter default and the app options that change it.
• Considers duty cycle and insertion delay, not just connectivity.
• Handles always-on clock branches through shutdown areas.

Follow-up Question & Model Response

"Why does a clock level shifter hurt duty cycle more than a data level shifter hurts timing?"

Candidate Model Response: A data path only cares about when the signal settles relative to one clock edge. A clock cares about both edges, and a level shifter often has different rise and fall delays. That difference moves one edge relative to the other, so the high phase grows or shrinks. For half-cycle paths or DDR interfaces, a few percent of duty-cycle error can eat the whole margin.