What is successive refinement of the UPF, and how does -update work?
From PDVerse Low-Power Physical Design Mentor Guide · pdVerse Mentor Guide
Short Answer
Successive refinement means power intent grows in layers: the IP provider writes constraint UPF, the integrator adds configuration such as strategies and control signals, and implementation adds supplies and cell detail. Each later layer refines earlier commands with -update instead of rewriting them, so an IP's constraints travel unchanged into every chip that uses it.
Technical Explanation
- Constraint UPF: atomic domains,
set_retention_elements(UPF) for state that must be kept, clamp values on ports, and legal power states without voltages. - Configuration UPF: the integrator adds isolation, level-shifter and retention strategies with control signals for this chip's use of the IP.
- Implementation UPF: supply sets and their association to domain handles, switches, isolation and retention supplies, and voltages.
- Refinable commands: the first call names the object; later calls in the same scope repeat the name (and domain, for strategies), add -update and only new arguments.
- Rules: -update on the first call is an error, a later call without it is an error, and a conflicting value for the same argument is an error.
- Deferred detail:
add_power_state(UPF) can define ON as FULL_ON with no voltage; ICC2 needs the value filled with -update before any action or check command. - Legacy form (still accepted by ICC2/PT):
create_pst(UPF) withadd_pst_state(UPF) for states, andset_isolation_control(UPF) for the control signal.
# [UPF] cop_constraint.upf (IP provider)
create_power_domain PD_COP -elements {.} -atomic -supply {primary}
set_retention_elements RL_COP -elements {u_regfile u_fsm}
set_port_attributes -elements {dbg_valid} -clamp_value 0
add_power_state PD_COP.primary -supply -state {ON -supply_expr {power == {FULL_ON}}}
# [UPF] mychip_config.upf (integrator)
set_isolation ISO_COP_OUT -domain PD_COP -elements {dbg_valid} -clamp_value 0 -isolation_signal ise -isolation_sense high
set_isolation ISO_COP_OUT -domain PD_COP -update -elements {irq_out}
# [UPF] mychip_impl.upf (implementation)
associate_supply_set SS_COP -handle PD_COP.primary
set_isolation ISO_COP_OUT -domain PD_COP -update -isolation_supply SS_AON
add_power_state PD_COP.primary -supply -update -state {ON -supply_expr {power == {FULL_ON 1.0}}}
# [ICC2] icc2_shell
load_upf mychip_top.upf
report_power_domainsWhat To Check
- Each layer lives in its own file with one owner.
- Every refining call repeats the object name and domain and uses -update.
- No later layer contradicts an earlier value, such as a clamp value.
- Deferred items such as state voltages are filled before implementation checks run.
Command Checks & Actions
create_power_domain PD_COP -elements {.} -atomic -supply {primary}Constraint layer: declare an atomic domain with an unassociated primary handle
set_isolation ISO_COP_OUT -domain PD_COP -update -isolation_supply SS_AONImplementation layer: add the isolation supply to the existing strategy
add_power_state PD_COP.primary -supply -update -state {ON -supply_expr {power == {FULL_ON 1.0}}}Fill the deferred ON voltage
load_upf mychip_top.upfRead all layers in order
report_power_domainsConfirm PD_COP, its elements and its primary supply after refinement
check_lp -stage upfCatch refinement errors such as a missing -update or a conflicting value
Healthy, Suspicious & Hard-stop Results
- Healthy (illustrative): All three layers load without errors, and
report_power_domainsshows PD_COP with SS_COP as its primary supply. - Suspicious (illustrative): A power state is still FULL_ON with no voltage when implementation starts.
- Hard stop: load_upf errors on a
set_isolationthat repeats ISO_COP_OUT without -update, or with a different clamp value.
Common Mistake
The Trap: Editing the IP provider's constraint UPF to add chip-specific strategies.
- The next IP drop overwrites the edits, and nobody can tell which rules came from the IP owner and which from the integrator.
What The Interviewer Is Testing
- Can you name the three layers and who owns each?
- Do you know the -update rules and what a refinable argument is?
Follow-up Question & Model Response
"Can you change an atomic domain's elements during refinement?"
Candidate Model Response: No. IEEE 1801 makes it an error to use -elements or -exclude_elements with -update on an atomic power domain, and an error to add -atomic with -update. You can still add supplies and compose it with other domains, but you cannot split it. That is what atomic means: the IP owner says this logic must power up and down as one unit.
Practical Example
Design Scenario: (illustrative) The COP IP team ships cop_constraint.upf: PD_COP is atomic, RL_COP names 2 retained blocks, and dbg_valid must clamp to 0. The MYCHIP integrator adds ISO_COP_OUT, controlled by ise active high, and later refines it with -update to add irq_out. Implementation associates SS_COP with PD_COP.primary, sets the isolation supply to SS_AON, and fills in the 1.0 V ON voltage the constraint layer left open. Three files, three owners, and not one line of the IP file changes between chips.
Low-Power & UPF Handbook
Master Low-Power VLSI & Multivoltage Design
Read the complete low-power guide library covering power domains, level shifters, isolation clamps, state retention, and UPF signoff verification.

Continue practising