Level 3 · Signoff Reasoning

Expert Low Power Interview Questions

Reason through multivoltage architecture, strategy precedence, feasibility checks, library mismatches, physical implementation, and signoff.

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Reason through multivoltage architecture, strategy precedence, feasibility checks, library mismatches, physical implementation, and signoff.

  1. 01 Walk through the complete "Mychip" multivoltage architecture — what are its power domains, and how do they relate to each other?Expert · Mychip is a full worked example that gives you a real four-domain chip instead of a toy two-domain sketch. PD_MYCHIP is the top-level, always-on 1.0V domain that wraps everything. Inside it sit three children: PD_CPU, an always-on 0.9V domain holding instance U_CPU; PD_COP, a 1.1V domain holding U_COP that can be fully shut down and therefore needs retention registers; and PD_DSP, a domain holding U_DSP whose supply is switched externally between 1.1V and 0.9V rather than by an on-chip switch. A Power Controller (U_PC) sits alongside these and drives the control signals that make shutdown/ retention/isolation actually happen: PSE (power switch enable), PSE_ACK (switch acknowledge), ISE (isolation enable) and SRE (save/ restore enable).
  2. 02 How is hierarchical UPF constructed for nested power domains, and what does create_composite_domain do?Expert · Nested domains are built the ordinary way — create_power_domain with -elements naming the sub-instances, and -scope steering where in the hierarchy the domain is rooted. On top of that, create_composite_domain lets you take several existing subdomains and fuse them into one logical composite domain that shares a single supply, which is useful when a set of subdomains should be treated as one unit for power-state or reporting purposes.
  3. 03 How does UPF define power-domain scope and extent, and what do the -applies_to_boundary options (upper/both/ lower) control?Expert · A power domain has two distinct notions: its scope, which is the hierarchy level that acts as the domain's root, and its extent, which is the actual set of design elements that belong to it. These are not the same thing — the scope just anchors where the domain lives in the hierarchy, while the extent is whatever you list with elements. Separately, when a domain has nested child domains, a strategy (isolation or level-shifter) needs to know which of the domain's boundaries it should apply to — the boundary facing the parent (upper), the boundary facing a contained child domain (lower), or both.
  4. 04 What does a TOP-level power-intent structure look like, using the Mychip example as a reference?Expert · A top-level power-intent file follows a consistent shape: declare the domains, then declare the supply nets reused across them, wire each domain's primary power/ground, and finally assemble a powerstate table on top. At the top, VDD1p0, VDDdsp, VDD0p9 and GND are created with -domain PD_MYCHIP -reuse so the same physical nets can be referenced again inside each subdomain without re-creating them.
  5. 05 What are supply-set relationships, and what does the resolve option of create_supply_net control?Expert · A supply set is an abstract collection of two functions — power and ground — accessed as SS.power/SS.ground, and it is domain- independent by default. Supply sets relate to each other through commands like associate_supply_set (ties the functions of two or more supply sets to the same net) and set_equivalent (marks supply sets as electrically equivalent). Separately, -resolve on create_supply_net specifies a custom resolution function, or the built-in keyword parallel, used when a net connects the internal PG pins of more than one macro that each have a fine-grained switch, or when the net is associated with a multi-driver supply-set group.
  6. 06 How does UPF represent illegal power states, and what mechanisms exist to declare them?Expert · UPF lets you flag certain combinations of supply states as simply not allowed to occur. The mechanism is the add_power_state command applied to a supply, group, or domain object: each named state carries a supply expression together with either a -legal or illegal tag, so the state table itself records which combinations are valid operating points and which are forbidden.
  7. 07 How does a power switch's control and acknowledgment signal pair work?Expert · A power switch is built with create_power_switch, given an input supply port, an output supply port, and a control port that drives it on or off. The on_state and off_state arguments define, as a boolean function of the control signal, when the output is powered and when it isn't. Optionally the switch can also report back through an ack_port: once the switch has settled into its commanded state, the ack line changes to confirm it, and ack_delay specifies how long after the control changes the acknowledge is expected to be valid.
  8. 08 What is the architectural difference between header and footer power switches, and when would each be used?Expert · A header switch sits between the power rail and the power supply pins of the power-down domain, cutting VDD to the domain. A footer switch instead sits on the ground side, cutting the connection between the domain's ground pins and the ground rail. Both accomplish the same goal — removing the supply path to shut a domain's leakage down — but they differ in which rail they interrupt.
  9. 09 How does a virtual rail behave differently from a primary rail inside a shutdown domain, using the Mychip PD_COP example?Expert · In PD_COP, the domain's primary power net is set to VDD1p0_SW — a supply net created specifically inside PD_COP (create_supply_net VDD1p0_SW -domain PD_COP) that is the switched output of the power switch. This is the rail that actually collapses when the domain shuts down. VDD1p0, by contrast, is the always-on input rail feeding the switch, and it stays up regardless of PD_COP's power state — it's deliberately used as the isolation_power_net and retention_power_net so that isolation clamps and retention storage keep working even while the switched (virtual) rail is dead.
  10. 10 What is retention supply architecture, and what does -retention_supply_net / -use_retention_as_primary control?Expert · A retention strategy is declared with set_retention -domain retention_power_net -retention_ground_net -elements, naming the always-on rail that backs up the listed state elements. UPF also provides a dedicated third net, -retention_supply_net, which lets you separate the retention backup supply out as its own distinct net rather than reusing the domain's primary or the isolation net; and -use_retention_as_primary, which flips this around and lets the retention supply itself be designated as the domain's primary supply.
  11. 11 What is the precedence order for isolation strategies when multiple strategies could apply to the same element?Expert · When more than one set_isolation strategy could apply to the same element, the tool resolves the conflict using a fixed precedence order, from highest to lowest: (1) strategies applying to ports explicitly via -elements, (2) strategies applying to ports implied by an instance named via -elements, (3) strategies applying to ports implied purely by the domain name, (4) strategies using -no_isolation, (5) strategies using both -source and -sink together (ranked above one using just one of the two), (6) strategies with -diff_supply_only true, and (7) strategies with -diff_supply_only false. When two strategies still tie, the tool keeps whichever strategy was created first and strips the overlapping elements out of the later one.
  12. 12 What are the advanced level-shifter placement strategies (self/parent/fanout/automatic/sibling), and how do you choose?Expert · set_level_shifter's -location option controls where the levelshifting cell physically sits relative to the domain boundary it's shifting. -location self places it inside the domain being shifted; -location parent places it in the parent domain; location fanout places a shifter at every sink fanout domain individually (useful when different fanout branches have heterogeneous supplies); and -location automatic lets the tool choose. UPF also adds -location sibling to this set for placement in a sibling domain, alongside an expanded location vocabulary (automatic, self, fanout, fanin, faninout, parent, sibling).
  13. 13 How is an always-on control network constructed, and what is the automatic inference rule for always-on cells?Expert · Always-on logic is needed wherever a signal must keep functioning even while the domain around it is shut down — retention registers, isolation cells, retention control paths, and isolation enable paths all fall into this category, and any save/ restore signal that has to physically pass through a shutdown voltage area needs an always-on buffer to carry it across. An always-on cell is functionally an ordinary cell (buffer/inverter) but with an added backup power supply that keeps operating continuously through shutdown. The automatic inference rule is that the tool will only perform always-on buffering/optimization if the target library actually contains always-on inverters/ buffers, and those library cells must be marked with the always_on attribute for the tool to recognize and use them.
  14. 14 Walk through the "smart-derive isolation strategy" gotcha for newly punched control ports — what goes wrong and how is it fixed?Expert · By default, whenever the tool punches a new hierarchical pin to carry a retention, switch, or isolation control signal down through the hierarchy, it automatically derives a -no_isolation strategy on that newly punched pin. That is normally the safe default. The problem arises when the driver of that control pin is actually LESS always-on than the control pin itself needs to be — in that situation the pin genuinely needs isolation, but no_isolation sits at the highest precedence level in the isolation-strategy resolution order, so there is no way to override it and add real isolation once the tool has already derived -no_isolation. The violation becomes unfixable through normal means.
  15. 15 How does analyze_mv_feasibility detect CLP-style violations when power management cells cannot be mapped to library cells?Expert · analyze_mv_feasibility (with -isolation, -enable_level_shifter, retention, or -level_shifter) checks whether the power management cells your UPF strategies call for can actually be mapped to cells available in the library. If a strategy's required isolation, enable-level-shifter, retention, or level-shifter cell cannot be mapped, the tool raises a UPF-909 error, the Tcl command returns status 0, and it produces a report of "Iso/Els cell mapping failures" or "Retention cell mapping failures" listing, per failing element: Element, Reside Domain, Strategy, Strategy Domain, Clamp, Sense, and Failure Reason.
  16. 16 What happens if an isolation cell has the wrong clamp value, and how would this surface during verification?Expert · set_isolation's -clamp_value option (0, 1, or latch) determines what value the isolated output is forced to when isolation is active: 0 uses an AND-gate-style clamp, 1 uses an OR-gate-style clamp, and latch holds whatever value the non-isolated port had at the moment isolation activated. If the clamp value specified doesn't match what the downstream logic actually expects when the domain is shut down, the isolated output will present the wrong constant (or a stale latched value) to always-on logic during shutdown — a functional correctness bug, not merely a mapping issue.
  17. 17 What happens if a retention strategy is given the wrong retention supply, and what UPF mechanism helps prevent this?Expert · If a retention strategy's -retention_power_net/retention_ground_net (or -retention_supply_net) points at a supply that is not genuinely always-on relative to the domain being retained, the retention latches lose power at the same time the domain shuts down and the saved state is corrupted — retention silently fails to do its job. UPF provides a correlation-check mechanism specifically for this: set_retention's -parameters option, with values RET_SUP_COR / NO_RET_SUP_COR (retention-supply correlation) and SAV_RES_COR / NO_SAVE_RES_COR (save/restore correlation), which lets the tool check the correlation between the retention supply and the related save/restore behavior.
  18. 18 What happens if save/restore signals have incorrect polarity, and what UPF assertion mechanism catches this?Expert · set_retention_control's -save_signal and -restore_signal each carry an explicit sense ({sig high} or {sig low}). If the declared sense doesn't match how the signal is actually driven, the retention register could save or restore at the wrong time — or worse, save and restore could both appear active simultaneously, which is logically incoherent. UPF provides a built-in consistency check for exactly this: set_retention_control's -assert_r_mutex, -assert_s_mutex, and assert_rs_mutex options, which assert that the save and restore signals are mutually exclusive — the clearest error-prevention mechanism available for retention correctness.
  19. 19 What are library-definition problems or UPF-tolibrary mismatches, and what command reconciles a cell's actual power pins with UPF's abstract model?Expert · UPF's abstract supply-set model doesn't automatically know which physical pin on a real library cell corresponds to which logical supply function. set_pin_related_supply -pins -related_power_in related_ground_pin is the command that reconciles this: it explicitly ties a cell's actual physical power/ground pins to the abstract UPF supply model, which matters directly for librarydefinition problems and UPF-to-library mismatches. Related failure modes include map_retention_clamp_cell, which is not actually a valid UPF command and causes an error at load_upf if present in a UPF file, and the pin-name-matching mechanism used to auto-infer complex retention cells, which can fail to find a match and requires manual association via define_user_attribute/ set_attribute with the retention_equivalent attribute.
  20. 20 What does physical implementation and signoff look like for a multivoltage design (secondary PG placement constraints, check_mv_design, Early Data Check policies)?Expert · Physical signoff for an MV design centers on three pieces: secondary PG placement constraints, which govern where power-management cells (level shifters, isolation cells, enable level shifters, repeaters, retention registers, tie cells) are allowed to sit relative to secondary power/ground straps; check_mv_design, the complete power-intent and PG-connectivity/ electrical-correctness check that can be restricted with isolation or -pg_pin; and the Early Data Check Manager, which lets you set a global severity policy (strict, lenient, or normal) or a per-check policy (error, tolerate, or repair) and then report results with report_early_data_checks.