Synthesis says 120 mW and signoff says 165 mW. How do you find the gap?

Short Answer

Synthesis power has an ideal clock, estimated wire capacitance and often different activity, so it is expected to read low. Find the gap by running both netlists through the same corner and activity file and comparing report_power -groups (PT) group by group, then check clock network, wire capacitance, glitch, annotation and leakage in turn, one cause at a time.

Technical Explanation

• Clock tree: synthesis sees an ideal clock with no buffers; after CTS, clock buffers and wires are often among the largest groups.
• Wire capacitance: synthesis estimates it; extracted parasitics after routing are usually higher on long nets, which raises switching power.
• Glitch: zero-delay activity propagation misses glitches; a timed gate-level simulation shows them.
• Activity annotation: a different SAIF, a broken name mapping after optimization, or lower annotation coverage shifts every group at once.
• Leakage and Vt mix: timing fixes after synthesis swap cells to faster, leakier flavours and add hold buffers.
• Method: same corner, same mode voltage and same activity file for both reports, before you blame the flow.
• What breaks: optimizing logic when most of the gap is the clock tree wastes weeks and leaves the real cause in place.

# [PrimeTime]  pt_shell
set_app_var power_enable_analysis true
read_saif video_1080p.saif
update_power
report_power -groups {register combinational sequential}

What To Check

• Both reports use the same corner, the same mode voltage and the same activity file.
• Annotation coverage is similar in both runs; a drop at signoff points to name mapping.
• Clock network power at signoff against whatever clock estimate synthesis used.
• Glitch contribution from a timed gate-level run on the worst blocks.

Healthy, Suspicious & Hard-stop Results

• Healthy (illustrative): After adding a clock-tree estimate to synthesis, the gap is under 10% and each group differs by a few mW.
• Suspicious (illustrative): Clock network explains half the gap, but combinational power also rose 15% with the same SAIF.
• Hard stop: Annotation coverage fell from 96% at synthesis to 60% at signoff, so the two runs used different activity.

What The Interviewer Is Testing

• Can you list what synthesis power cannot see, and where each item shows up in a report?
• Do you control corner and activity before comparing numbers?

Follow-up Question & Model Response

"Should synthesis power ever match signoff exactly?"

Candidate Model Response: No, and an exact match often means both runs share the same wrong assumption. Synthesis power is for relative decisions such as architecture, clock gating and Vt mix, where a consistent bias does no harm. What you want is a stable, explained ratio across blocks and releases. When that ratio suddenly moves for one block, that is the moment to dig in.