What is a power state table?
From PDVerse Low-Power Physical Design Mentor Guide · pdVerse Mentor Guide
Definition
A power state table (PST) is a structured list of the legal voltage/state combinations a design's supplies can be in — created in UPF with create_pst and populated with add_pst_state — used to formally define which supply-value combinations across all domains are valid operating modes.
Mentor Explanation
A beginner might assume each power domain's state is independent, but a PST is precisely the mechanism for describing valid combinations across the whole chip at once — because not every combination of 'domain A is on, domain B is off, domain C is at low voltage' is necessarily a mode the design actually supports. Think of it this way: it's a truth table of legal chip-wide power modes.
Example
A representative power state table shows four PST states across three supplies (VDDG, VDD_ON, VDD_SW): e.g., PST1 = {0.8, 1.0, 1.0} while PST3 = {0.8, 1.0, off} — the same VDDG and VDD_ON values, but VDD_SW switched off in PST3.
Why It Matters
A power state table is what downstream analysis and verification (like checking isolation/levelshifter completeness) uses to know which combinations of domain states are actually reachable and legal, versus which are meaningless or erroneous.
Command
create_pst -supplies {port list}
add_pst_state -pst -state {values}Common Beginner Mistake
A beginner mistake is treating each domain's on/off/voltage state as something to reason about in isolation — without a PST tying them together, tools have no way to know that, say, 'PD_COP off while PD_MYCHIP is also off' isn't a state the chip is ever supposed to enter.
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