What is the antenna effect?
From PDVerse PnR Interview Handbook · pdVerse Mentor Guide
Short Answer
The antenna effect is damage to a transistor's gate oxide during manufacturing, not during operation. While the chip is being built layer by layer, a long wire connected only to a gate collects electrical charge from the plasma etch steps. With no driver connected yet to drain that charge away, it can discharge through the thin gate oxide and damage it permanently.
Technical Explanation
- Metal layers are built one at a time from the bottom up. When metal N is being etched, anything that connects through higher layers does not exist yet.
- Plasma etching deposits charge on exposed metal. A wire connected to a transistor gate, but not yet connected to any diffusion such as a driver output, has nowhere to send that charge except through the gate oxide.
- The longer or larger the wire, the more charge it collects, like a bigger antenna picking up more signal. That is where the name comes from. It is also called plasma-induced or process-induced damage.
- The risk is judged by a ratio: the area (or perimeter) of connected metal divided by the area of the gate it connects to. If the ratio is above the foundry limit for that layer, the gate is at risk.
- Once the net is fully connected, the driver's diffusion gives the charge a safe path. So the danger is only for metal that connects to a gate before the layer that connects it to the driver.
- Antenna rules are coded into the technology data and the cell library's antenna properties. Zroute checks and fixes them during detail routing, and
check_routesreports any that remain. - The two standard fixes are layer hopping, which breaks the long wire so less metal connects to the gate at the risky step, and diode insertion, which gives the charge a safe path to the substrate.
- Some antenna rules count the sidewall area of the metal rather than its top surface, and some add up the metal on all layers below the one being etched. The foundry chooses the method; the tool follows whatever the antenna rule in the technology data says.
Common Mistake
The Trap: Assuming antenna violations are just DRCs and can be waived like a minor spacing error. An antenna violation predicts real oxide damage, which shows up as a weak or leaky gate. A waived antenna violation can pass every signoff check and still fail reliability testing on silicon.
Follow-up Question & Model Response
"Why does the violation depend on which layer the driver connects on?"
Candidate Model Response: The gate is only at risk while its wire is connected to it but not yet to a driver. If the driver joins the net on M2, then during M3 and higher etches the charge already has a safe path, so only M1 and M2 metal counts. If the driver only joins on M5, then M1 to M4 metal attached to the gate is all exposed at some step. So the fix often moves the connection to the driver lower or breaks the wire near the gate.
Practical Example
Tapeout Scenario: A small gate with 0.05 um² of oxide connects through a 400 um M2 wire to its driver, which only joins the net through an M5 connection (illustrative). During the M2 etch, all 400 um of M2 is attached to the gate and nothing else. If the M2 wire is 0.06 um wide, that is 24 um² of metal against 0.05 um² of gate, a ratio of 480. With a layer limit of 400, the net is flagged. Adding a short jump up to M3 about 5 um from the gate means only those 5 um of M2 stay attached to the gate during the M2 etch, and the rest joins later, bringing the ratio down to about 6.
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