Level 1 · Foundations

Beginner PnR Interview Questions

Build solid foundations in physical design inputs, standard cell models, technology data, units, and manufacturing grids.

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Build solid foundations in physical design inputs, standard cell models, technology data, units, and manufacturing grids.

  1. 01 What are the main inputs required for physical design?Beginner · Physical design needs connectivity, cell models, process rules, timing requirements, and physical intent. These inputs jointly tell the tool what to build, what resources it can use, where things may go, and how fast the result must operate.
  2. 02 What does a gate-level netlist contain?Beginner · A gate-level netlist describes the circuit as instances of cells or modules connected by nets. It captures logical connectivity, rather than the final physical locations and wire shapes.
  3. 03 How is RTL different from the netlist used for place and route?Beginner · RTL expresses intended register-transfer behavior; a mapped netlist expresses an implementation using particular cells. Place and route needs concrete cell models to place instances and evaluate their timing.
  4. 04 What information does a Liberty timing library provide?Beginner · A Liberty library describes how cells behave electrically and logically under characterized conditions. It supplies information for timing, power analysis, and legal cell selection; it is not a placement drawing.
  5. 05 What is the difference between LEF and DEF?Beginner · LEF describes reusable technology and cell physical abstractions; DEF describes the physical state of a particular design. One defines the building blocks and rules, while the other records how instances are arranged in a design.
  6. 06 What are NDM, reference libraries, and design libraries in ICC2?Beginner · NDM is ICC2's library/database framework. Reference libraries supply reusable blocks such as standard cells and macros; a design library stores the implementation blocks you are working on and their associated technology and reference setup.
  7. 07 What does the technology file contain, and why is it necessary?Beginner · Technology data defines the physical vocabulary and implementation rules of the process: units, layers, vias, placement sites or tiles, and applicable routing information. It allows geometry to have consistent meaning.
  8. 08 What is SDC, and what should a physical-design SDC contain?Beginner · SDC expresses timing intent and the external electrical environment through constraint commands. It tells timing analysis which clocks and paths matter, and under what assumptions they should be checked.
  9. 26 Which units are used in physical design, timing, and power?Beginner · A number has engineering meaning only when its unit is known. Physical design combines distance, time, capacitance, resistance, voltage, current, and power, and the units can differ between files and reports.
  10. 27 What are database units, and how do you convert DEF coordinates?Beginner · Database units, or DBU, represent physical coordinates as integers. A DEF declaration of 2000 database units per micrometer means that 2000 coordinate units represent a physical distance of 1 um.
  11. 28 What is the difference between wire width, spacing, and pitch?Beginner · Width is the thickness of a wire measured across it. Spacing is the edge-to-edge gap between neighboring shapes. Pitch is the center-to-center distance between repeating features, such as parallel routing tracks.
  12. 36 What is the purpose of the pre-floorplan sanity gate?Beginner · It decides whether the imported, linked logical design and its timing intent are trustworthy enough to begin floorplanning; it does not judge placement or timing quality-of-results.
  13. 37 Which inputs must a physical-design engineer verify at this gate?Beginner · Verify the synthesised gate-level netlist, SDC, top name, handoff revision, logical libraries, reference/technology setup, modes, corners, scenarios, and available synthesis or STA summaries.
  14. 38 Why record a manifest and file checksums?Beginner · A manifest connects every loaded file to a revision, producer, timestamp, mode, corner, and checksum so the run can be reproduced.
  15. 39 How do you confirm the correct top module and netlist revision?Beginner · The current block, expected top name, hierarchy, and inventory must agree with the handoff record and synthesis summary.
  16. 40 Why check libraries and units before reading timing numbers?Beginner · Library identity and user units determine how cell behaviour and numeric constraint values are interpreted.
  17. 41 What is the difference between importing and linking a netlist?Beginner · Import creates design objects from the Verilog; linking resolves every instantiated reference against the available design and library context.
  18. 42 Why must current_block be checked before every sanity run?Beginner · Most ICC2 queries and reports operate on the current block, so correct syntax in the wrong context gives a polished but wrong answer.
  19. 43 What does an unresolved reference mean?Beginner · An instance requests a module or library cell definition that the active reference context cannot supply.
  20. 44 When can a black box be intentional?Beginner · A black box is acceptable only when the methodology deliberately abstracts its internals and still provides a controlled interface for timing and implementation.
  21. 45 What does check_netlist contribute before floorplanning?Beginner · It checks structural consistency such as connectivity defects that can survive parsing and linking.
  22. 46 How should undriven and unloaded objects be reviewed?Beginner · An undriven object lacks a valid source; an unloaded output drives nothing. Either can be intentional at a boundary or evidence of lost connectivity.
  23. 47 What is the difference between a dangling connection and a no-load net?Beginner · A dangling pin or port is disconnected at an interface, while a no-load net has a driver but no meaningful sink; both require context.
  24. 48 Why are multiply driven nets a hard structural concern?Beginner · Multiple active drivers can make a net functionally ambiguous unless an intentional bus or tri-state model explains them.
  25. 49 Why inspect constant-driven pins and nets?Beginner · Constants can be correct mode straps or evidence that logic, a clock, or an enable was optimised away unexpectedly.
  26. 50 Which logical counts should be reconciled?Beginner · Compare ports, hierarchical cells, sequential cells, combinational cells, memories/macros, nets, and references with the synthesis handoff.
  27. 51 Why inspect hierarchy before applying SDC?Beginner · SDC object paths depend on the post-synthesis hierarchy and naming that ICC2 actually loaded.
  28. 52 Why can a syntactically valid SDC still be wrong?Beginner · Syntax validation proves commands can be parsed; it does not prove objects resolve, values model the interface, or constraints enter the correct mode/scenario.
  29. 53 What does an empty collection during SDC loading indicate?Beginner · A selector found no current design objects, commonly because hierarchy, names, buses, or optimisation changed.
  30. 54 What must be checked for a primary clock?Beginner · Verify its source object, name, period, waveform, mode visibility, and reach to intended sequential clock pins.
  31. 55 What is a virtual clock and why is it used?Beginner · A virtual clock has no physical design source and commonly represents an external launch or capture reference for I/O timing.
  32. 56 What makes a generated clock different from a primary clock?Beginner · A generated clock derives its frequency, phase, or edges from a master/source relationship in the implemented logic.
  33. 57 What do input and output delays describe?Beginner · They describe external timing relative to a clock; they are not delays of the block's input or output buffers.
  34. 58 Why check driving cell, input transition, and output load?Beginner · These constraints model the electrical environment needed for meaningful cell delay and slew calculation at ports.
  35. 59 What does check_timing check at this stage?Beginner · It diagnoses missing or inconsistent timing setup such as no-clock points, unconstrained endpoints, loops, generated-clock issues, and other selected categories.
  36. 60 What evidence is required before beginning floorplanning?Beginner · Readiness requires matched provenance, resolved linking, classified structural findings, applied and reviewed SDC, complete clock/I/O intent, active scenario coverage, and owned waivers.
  37. 116 What is a floorplan, and what problem does it solve?Beginner · A floorplan turns a logically valid design into a physical plan for boundaries, rows, macros, pins, channels, and reserved resources. It is the first proof that the design can plausibly fit and connect.
  38. 117 How do die, core, and core offset differ?Beginner · The die is the outer design boundary; the core is the region used for standard-cell rows and most implementation objects. Core offsets are the distances from die sides to core sides.
  39. 118 Which area categories must be separated before calculating a floorplan?Beginner · Separate standard-cell area, hard-macro area, fixed or physical-only cell area, placeable area, reserved area, and whitespace. Mixing them makes utilisation meaningless.
  40. 119 What are whitespace and target utilisation?Beginner · Whitespace is the placeable area left after counted cells are assigned area. Target utilisation is the planned fraction of placeable area occupied by the explicitly counted objects.
  41. 120 How do you estimate required placeable area from target utilisation?Beginner · Divide the counted placeable object area by the declared target utilisation. The result is a mathematical starting point, not a final implementable core.
  42. 121 How do target, effective, and local utilisation differ?Beginner · Target utilisation is an input assumption; effective utilisation is the achieved counted occupancy after exclusions; local utilisation measures a smaller region. They answer different questions.
  43. 122 What is core aspect ratio?Beginner · Core aspect ratio is width divided by height. Equal-area rectangles can have different aspect ratios and very different routing and timing behaviour.
  44. 123 How do you derive rectangular core width and height from area and aspect ratio?Beginner · For area A and aspect ratio AR = width/height, width is sqrt(A x AR) and height is sqrt(A / AR). Keep units through every step.
  45. 124 How do asymmetric offsets change die dimensions?Beginner · Add the actual left and right offsets to core width, and the actual bottom and top offsets to core height. Do not double one offset unless both sides are truly equal.
  46. 125 How do sites, rows, and routing tracks differ?Beginner · A site defines legal placement increments, a row repeats sites for standard cells, and a routing track defines candidate wire centre lines. A row is not a track.
  47. 126 Why do row orientation and fragments matter?Beginner · Row orientation must support the library’s legal cell orientations and power-rail alignment. Tiny row fragments consume bookkeeping space but may be unusable for real cells.
  48. 127 How does a hard macro differ from a standard cell during floorplanning?Beginner · A hard macro has fixed dimensions and pin geometry, so its placement strongly shapes channels and rows. Standard cells are small, numerous, and placed later within legal rows.
  49. 128 What should drive initial macro placement?Beginner · Connectivity, dataflow, timing criticality, I/O affinity, bus sharing, clock/reset sources, power domains, pin sides, and macro dimensions should drive placement.
  50. 129 Why do macro orientation and alignment matter?Beginner · Orientation changes which side the pins face; alignment determines whether the macro sits on required grids. A geometrically legal rotation can still damage dataflow or power access.
  51. 130 What makes a macro channel usable?Beginner · A channel is usable only when its width and geometry support signal tracks, facing pins, power straps, vias, shielding, buffers where needed, and technology spacing.
  52. 131 How does a macro halo differ from a placement blockage?Beginner · A keepout margin moves with its macro; a placement blockage is a fixed floorplan region. Both reserve space, but ownership and affected objects differ.
  53. 132 What are boundary, end-cap, and corner cells?Beginner · Core boundary cells protect and complete standard-cell row edges; inside/outside corner cells handle core or voltage-area corners; I/O-ring corner cells belong to the pad ring. They are different library functions.
  54. 133 How do chip I/O, top-level ports, macro pins, and block pins differ?Beginner · Chip I/O pads or bumps connect the die to the package; top-level terminals represent design connections; macro pins belong to fixed macros; block pins expose hierarchical interfaces.
  55. 134 What is a feedthrough?Beginner · A feedthrough is a signal that enters a block and leaves it without being logically consumed there. It may shorten a top-level route, but it spends pin, routing, and possibly buffering resources inside the block.
  56. 135 What does early congestion mean?Beginner · Early congestion estimates compare routing demand with available capacity in coarse regions. Overflow means demand exceeds capacity on one or more routing resources.
  57. 136 What is the difference between a legal pin and an accessible pin?Beginner · A legal pin obeys placement rules; an accessible pin also has a usable routing approach on an allowed layer and track without blockage or spacing conflict.
  58. 137 Why reserve power-grid resources during floorplanning?Beginner · Rings, straps, rails, and vias consume area and routing capacity. Reserving their corridors early prevents a signal channel or pin plan from depending on tracks that power will later occupy.
  59. 138 How does a power domain differ from a voltage area?Beginner · A power domain describes logical power intent; a voltage area is the physical region where its cells may be placed. They are related but not interchangeable.
  60. 139 How can a floorplan affect timing before placement is complete?Beginner · Distance, macro pin side, detours, hierarchy crossings, feedthroughs, congestion, buffering opportunity, and clock-source location change estimated interconnect delay.
  61. 140 What evidence makes an initial floorplan reviewable?Beginner · A reviewable floorplan has deliberate boundaries, utilisation, usable rows, justified macro locations, feasible channels, constrained pins, early congestion/timing evidence, PG reservation, voltage-area legality, classified findings, and reproducible write-out.