ExpertQuestion 275 of 111Source PDF page undefined

What is a clock balance group actually for, and why can't the tool balance skew between a generated clock and its master automatically?

From PDVerse PnR Interview Handbook · pdVerse Mentor Guide

Short Answer

A clock balance group is a set of clocks considered together for delay balancing, created with create_clock_balance_group and optionally explicit per-clock offset_latencies. derive_clock_balance_constraints auto-identifies clocks with interclock timing paths worse than a threshold, and balance_clock_groups actually performs the balancing. The one hard limit: the tool cannot balance skew between a generated clock and other clocks -- a generated clock's relationship to its master is already fully determined by the generation relationship itself, not something interclock balancing can independently adjust.

Technical Reference DiagramWhat is a clock balance group actually for, and why can't the tool balance skew between a generated clock and its master automatically?
What is a clock balance group actually for, and why can't the tool balance skew between a generated clock and its master automatically?, illustrating the physical design concept.

Technical Explanation

  • A clock balance group is a set of clocks considered together for delay balancing -- created via create_clock_balance_group, with an optional -offset_latencies list for explicit per-clock targets rather than the default zero-offset goal.
  • derive_clock_balance_constraints automatically identifies clocks with interclock timing paths, by default considering all such paths; -slack_less_than restricts it to paths worse than a specific threshold.
  • balance_clock_groups performs the actual balancing; for MCMM designs it balances across all active scenarios, not just the current one.
  • The hard limit: the tool cannot balance skew between a generated clock and other clocks -- a generated clock's relationship to its master is already fully determined by the generation relationship (divide_by, edges, etc.), so there's no independent skew for interclock balancing to adjust.

Formula Or Decision Rule

create_clock_balance_group -> derive_clock_balance_constraints (or manual grouping) -> balance_clock_groups. Default goal: zero delay offset, matching the longest insertion delay, unless -offset_latencies specifies otherwise.

What To Check

  • Warning sign: create_clock_balance_group is applied to a set including a generated clock and its master, expecting balance_clock_groups to adjust the relationship between them.
  • Inspect: confirm the documented limitation -- the tool cannot balance skew between a generated clock and other clocks.
  • Correct: adjust the generated clock's relationship via its own generation constraints [SDC: create_generated_clock options], not via interclock balancing.

Command Checks & Actions

ICC2create_clock_balance_group -name group1 -objects [get_clocks {clk1 clk2}]

Defines a balance group for genuinely independent clocks.

ICC2derive_clock_balance_constraints -slack_less_than -0.2

Auto-identifies clocks needing balancing based on real interclock path slack.

ICC2balance_clock_groups

Performs balancing across all active scenarios for MCMM designs.

Healthy, Suspicious & Hard-stop Results

  • Expected: balance groups contain only genuinely independent clocks (not a generated clock paired with its own master), and balance_clock_groups converges to the target offsets.
  • Investigate: a balance group including a generated clock and its master shows no meaningful change after balance_clock_groups -- this is expected given the documented limitation, not a bug to keep re-running against.
  • Stop: repeated attempts to balance a generated clock against its master via clock balance groups, with no result -- stop and use the generated clock's own SDC definition to adjust the relationship instead.

Common Mistake

The Trap: Trying to use a clock balance group to fix skew between a generated clock and its master -- that relationship is already fixed by the generation definition itself, and balance_clock_groups cannot override it.

What The Interviewer Is Testing

Whether you know the specific limitation (generated clocks can't be interclock-balanced) rather than assuming clock balance groups are a universal skew-fixing tool.

Practical Example

Debug Scenario: A generated clock (divide-by-2 from a master) and its master are added to the same clock balance group hoping to reduce skew between them. balance_clock_groups makes no meaningful change -- because, per the documented limitation, the tool cannot balance skew between a generated clock and other clocks; that relationship needs to be addressed through the generated clock's own definition instead.

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