Why does inserting buffers along a long clock wire actually reduce delay instead of just adding more delay?

Short Answer

A long wire's propagation delay is dominated by RC and grows with the square of length: t = rcL^2/2. Splitting that wire into N equal segments with a buffer between each one reduces the wire-delay term quadratically -- t = rc(L/N)^2 + (N-1)t_b -- so even though you're adding N-1 buffer delays, the L^2-to-(L/N)^2 reduction more than pays for it once N is large enough. Setting the derivative to zero gives the optimal buffer count: N = Lsqrt(rc/t_b).

Technical Explanation

• A long wire's propagation delay from RC is t = rcL^2/2 -- the L^2 term means delay grows with the square of length, not linearly.
• Splitting the wire into N equal sections with a buffer at each junction changes the formula to t = rc(L/N)^2 + (N-1)*t_b -- the wire-delay term drops quadratically with N, while the buffer-delay term only grows linearly.
• Because one term drops quadratically and the other only grows linearly, adding buffers genuinely reduces total delay up to a point -- this is algebra, not a rule of thumb.
• Setting the derivative of total delay with respect to N to zero gives the optimal buffer count: N = L*sqrt(rc/t_b).
• Tapering buffers don't need to be identical -- drive strength can increase monotonically by a factor alpha per level (alpha^0d, alpha^1d, alpha^2*d, ...) to match the growing load as the tree fans out.
• report_clock_qor -type latency shows the tool-measured insertion delay for a live tree, letting you compare it directly against the t = rc(L/N)^2 + (N-1)t_b formula's prediction.

Formula Or Decision Rule

Undivided wire delay: t = rcL^2/2. Segmented (N buffers) wire delay: t = rc(L/N)^2 + (N-1)t_b. Optimal buffer count: N = Lsqrt(rc/t_b) (from setting dt/dN = 0). Decision rule: increase N toward this optimum while the quadratic wire-delay reduction still outweighs the added linear buffer delay; beyond it, more buffers cost more than they save.

Follow-up Question & Model Response

"What property must a clock buffer have that a normal data-path buffer doesn't need as strictly?"

Candidate Model Response: Equal rise and fall delay time -- clock buffers need this to preserve duty cycle and avoid clock pulse-width degradation as the signal propagates; a normal data buffer has no duty-cycle requirement to protect. Since perfect rise/fall balance is hard to guarantee, inverters are often used instead of buffers for clock tapering.