BeginnerQuestion 170 of 187Source: Synopsys ICC2 Implementation User Guide: Chip Finishing and Design for Manufacturing (Inserting Filler Cells)

Decap fillers vs plain fillers: why not use decaps everywhere?

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Short Answer

A decap filler is a capacitor between VDD and VSS that supplies local charge when nearby cells switch, which reduces dynamic voltage drop. A plain filler only keeps rails and wells continuous. Decaps are not free: each one leaks, and with modern thin gate oxides that leakage adds up, so at the finishing stage you place decaps where dynamic IR needs them and plain fillers elsewhere.

Technical Reference DiagramDecap fillers vs plain fillers: why not use decaps everywhere?
Schematic of a decap cell as a capacitor between VDD and VSS near a switching cell, supplying local charge during a current spike, with a small leakage current arrow through the decap and a plain filler shown beside it with no connection between rails.

Technical Explanation

  • A decap is usually a MOS capacitor: a transistor with its gate on one supply and source-drain on the other. When a cluster of cells switches, it draws current in a spike; the decap supplies part of that charge locally, so less has to come through the grid resistance and inductance.
  • The cost is leakage. The gate oxide of a MOS capacitor leaks, and the leakage scales with capacitor area. Filling every empty site with decaps adds standby power that shows up on every die, all the time.
  • This page is about the finishing-stage choice of what goes into leftover row space. The earlier decision of where to reserve decap area during placement is covered in the decap placement page.
  • Decap fillers usually contain metal, so in the standard ICC2 flow they belong to the metal-filler step: they go in with create_stdcell_fillers (ICC2) first, violating ones are removed with remove_stdcell_fillers_with_violation (ICC2), then nonmetal plain fillers fill what is left.
  • The mix can be controlled. -type_utilization (ICC2) sets the percentage of each filler type, for example a split between ULVT and LVT decap groups, and -fill_remaining (ICC2) fills leftover gaps with the other cells in the list.
  • Leakage-aware selection exists too. -leakage_vt_order (ICC2) lists threshold-voltage layers in order of decreasing leakage so the command picks the lowest-leakage filler that still meets legalization; it needs the advanced legalizer enabled.
  • Decap fillers also bring metal and diffusion shapes into the row, so they can create DRC violations that plain fillers would not. That is why the guide removes violating metal fillers, sometimes over several passes, before plain fillers fill whatever remains. A decap-heavy mix therefore often ends with fewer decaps placed than planned.
  • The right amount comes from dynamic IR analysis, not a rule of thumb. Put decaps near hotspots, check the drop again, and use plain fillers where the drop already has margin.

Common Mistake

The Trap: Using the decap filler as the only filler everywhere "for extra margin". Dynamic IR improves by a few millivolts in areas that were already fine, while block leakage at the hot corner rises by 18%. The chip misses its standby power target, and removing decaps after signoff means reopening DRC, LVS and rail analysis. The better sequence is to place decaps where dynamic IR shows a need, then fill the rest with plain or low-leakage fillers, and to compare leakage before and after the filler step as part of the finishing checklist.

Follow-up Question & Model Response

"How would you decide how much decap filler to use in a block?"

Candidate Model Response: I would start from dynamic IR results and look at where the drop exceeds budget and how much margin other regions have. I would put decap fillers into the hotspot regions first, rerun dynamic analysis, and stop adding once the worst drop is inside budget with some margin. Everywhere else gets plain or low-leakage fillers. I would also check leakage at the worst-leakage corner before and after, because that is the cost I am trading against.

Practical Example

Tapeout Scenario: A block has 900,000 empty sites after the final ECO (illustrative). Filling all of them with decap fillers adds about 1.8 nF and cuts worst dynamic drop from 92 mV to 71 mV, but adds 2.4 mW of leakage at the hot corner. Filling only the 22% of sites inside hotspot regions adds about 0.4 nF, brings the worst drop to 76 mV against an 80 mV budget, and adds 0.5 mW. The rest are plain fillers. The team records both numbers, drop and leakage, in the signoff report so the trade-off is visible to the power owner.

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