What does set_dont_touch_network actually protect by default, and how does -clock_only narrow that scope?
From PDVerse PnR Interview Handbook · pdVerse Mentor Guide
Short Answer
By default, set_dont_touch_network [get_clocks CLK] protects BOTH clock paths AND clock-as-data paths -- meaning a clock signal used somewhere as an ordinary data input is also protected. -clock_only narrows that to just the clock paths, leaving clock-as-data usage open to optimization. -clear removes the protection entirely.
Technical Explanation
- By default, set_dont_touch_network [get_clocks CLK] protects BOTH clock paths AND clock-as-data paths -- a broader scope than just "the clock tree."
- Clock-as-data paths means a clock signal used somewhere in the design as an ordinary data input, not as a clock -- the default behavior protects that usage too.
- -clock_only narrows the protection to just the genuine clock paths, leaving any clock-as-data usage open to normal optimization.
- -clear removes the dont_touch_network protection entirely, returning the clock network to normal optimization eligibility.
Common Mistake
The Trap: Assuming set_dont_touch_network only protects the clock tree itself -- by default it also protects any clock-as-data usage, which is broader than many people expect until they check.
Follow-up Question & Model Response
"Why might a design legitimately want to optimize a clock-as-data path even while keeping the true clock network protected?"
Candidate Model Response: Because a clock signal used as ordinary data (e.g. feeding a frequency-detection circuit) is functionally just a data signal at that point, and forcing it to stay unoptimized purely because its SOURCE happens to be a clock can leave real timing or area improvement unclaimed on that specific path.
Practical Example
Debug Scenario: A design uses a clock signal as a data input to a frequency-monitoring block elsewhere. Using the default set_dont_touch_network protects both the real clock tree AND this data usage -- switching to -clock_only lets the frequency-monitoring path be optimized normally while the actual clock tree stays protected.
Physical Design & Planning Handbook
Master ASIC Physical Design Planning & Floorplanning
Dive into 14 comprehensive chapters covering netlist sanity, FinFET grids, macro placement, power grids, CTS, and timing budgeting.
Continue practising