What ECO techniques are available after CTS if a hold violation shows up, and when do you use freeze-silicon ECO instead of a normal buffer insertion?

Short Answer

For a normal post-CTS hold fix, add_buffer_on_route inserts a buffer directly on the existing route topology, or size_cell resizes an existing cell -- both are logic/metal-only changes to an already-placed, already-routed design. Freeze-silicon ECO is a different tier: it maps the fix onto pre-placed programmable spare cells (matched by psc_type_id) so the change requires only a metal-mask respin, not a full new mask set -- used specifically when the design has already taped out or is close enough that touching silicon layers is unacceptable.

Technical Explanation

• For a normal post-CTS hold fix, add_buffer_on_route inserts a buffer directly on the existing route topology to minimize disturbance, and size_cell resizes an existing cell -- both are straightforward logic/metal changes on an already-placed, already-routed design.
• Freeze-silicon ECO maps the fix onto pre-placed programmable spare cells (PSCs), matched to the ECO cell via the shared psc_type_id attribute.
• PSCs let an ECO be implemented as a metal-mask-only respin, since transistor-level (silicon) layers don't change -- only the metal wiring connecting pre-placed transistors differently -- a fraction of the cost and turnaround of a full new mask set.
• This is used specifically post-tapeout, or late enough that touching silicon layers is unacceptable -- not as a general substitute for normal ECO earlier in the flow.
• place_freeze_silicon places each ECO cell and maps it to the nearest matching spare cell; cells deleted by ECO changes remain in the design as converted spare cells rather than being removed, since removal would mean touching the silicon layer.
• check_freeze_silicon identifies ECO cells with no matching spare cell; create_freeze_silicon_leq_change_list generates a script mapping to a logically equivalent spare cell (a differently-named single spare cell, or up to two combined) when a direct match doesn't exist.

Formula Or Decision Rule

Normal post-CTS ECO (add_buffer_on_route / size_cell): use when the design has not yet reached mask-committed/tapeout-adjacent status -- no reason to constrain the fix to pre-placed spare cell capacity. Freeze-silicon ECO (place_freeze_silicon / map_freeze_silicon): use when touching silicon (implant/diffusion/poly) layers is unacceptable -- post-tapeout or equivalent late-stage constraint -- and the cost/turnaround of a metal-only respin is the deciding factor.

Healthy, Suspicious & Hard-stop Results

• Expected: check_freeze_silicon reports every needed ECO cell has a matching spare cell (direct or LEQ) before place_freeze_silicon runs.
• Investigate: check_freeze_silicon reports gaps -- resolve with create_freeze_silicon_leq_change_list before proceeding, rather than forcing a mismatched placement.
• Stop: a freeze-silicon fix would require an ECO cell type with no matching or LEQ-mappable spare cell anywhere in the design -- that fix cannot be done as metal-only and needs a different approach entirely, not a forced substitution.

What The Interviewer Is Testing

Whether you know WHY freeze-silicon ECO exists (metal-only respin cost, post-tapeout constraint) and can distinguish it from normal ECO, rather than treating both as interchangeable "fix a violation" tools.