Walk through a functional ECO from RTL fix to implemented layout.

Short Answer

Fix the RTL, produce a golden ECO netlist, and prove it matches the new RTL in Formality. In ICC2, eco_netlist -by_verilog_file (ICC2) compares that netlist with the layout netlist and writes the edits as Tcl, which you source, place with place_eco_cells -eco_changed_cells (ICC2) and route with route_eco (ICC2). Then prove the layout netlist again in Formality and close timing in PrimeTime.

Technical Explanation

• Step 1, RTL and ECO netlist: the designer fixes the RTL and a minimal-change netlist is produced. Keep the change small so unrelated logic is not resynthesized.
• Step 2, first check: Formality compares the new RTL (reference) with the ECO netlist (implementation) using match (FM) and verify (FM). A failure here means the netlist does not implement the fix.
• Step 3, apply: eco_netlist -by_verilog_file eco.v -write_changes eco_changes.tcl (ICC2) compares the working design with the golden netlist and writes netlist editing commands. By default it ignores physical-only cells, timing ECO changes such as resized cells and added repeaters, and power and ground differences, so earlier timing fixes survive.
• Step 4, place: source the change file, then place_eco_cells -eco_changed_cells (ICC2) places the cells whose eco_change_status marks them as changed and legalizes them to the closest free site.
• Step 5, route: add fillers back where needed, then route_eco (ICC2) runs global routing, track assignment and detail routing on open nets. By default it is timing and crosstalk driven, so it extracts and updates timing first.
• Step 6, second check: write the layout netlist and run Formality again against the fixed RTL or the golden ECO netlist. This catches a wrong edit or a timing ECO that broke logic.
• Step 7, timing: extract, run PrimeTime, and fix any new violations with a timing ECO. Physical checks for DRC and LVS follow before signoff.

What To Check

• Formality passes on the ECO netlist before anything touches the layout.
• The change file size and contents match the intended fix.
• Every changed cell placed and legal, and no open nets after route_eco (ICC2).
• Formality passes on the layout netlist.
• PrimeTime clean in all signoff scenarios.

Healthy, Suspicious & Hard-stop Results

• Healthy (illustrative): Formality passes both times, 40 cells changed, all placed within 2 um, no opens, timing clean.
• Suspicious (illustrative): The change file edits far more cells than the RTL fix explains.
• Hard stop: Formality fails on the layout netlist, or the change file removes timing buffers because the timing option was turned on.

What The Interviewer Is Testing

• Can list the stages in order with the tool for each.
• Knows eco_netlist (ICC2) ignores timing ECO changes by default and why.
• Checks equivalence twice, before and after implementation.

Follow-up Question & Model Response

"When would you use -extract_timing_eco_changes with eco_netlist?"

Candidate Model Response: Only when the golden netlist already contains the timing changes you want, for example a netlist written out after timing fixes were made elsewhere. Then the option makes eco_netlist (ICC2) apply resized cells and added or removed repeaters as well as the functional edits. If the golden netlist came fresh from synthesis, it has none of the layout's timing buffers, and turning the option on would try to remove them. That undoes closure work, so the default ignores them.