What does it actually mean for gain-based (logical effort) optimization to "maintain equal gain per stage," and why is that the goal?
From PDVerse PnR Interview Handbook · pdVerse Mentor Guide
Short Answer
During gain-based optimization, the algorithm computes the gain of each cell along the critical path and tries to maintain equal gain for each stage -- equal gain per stage is optimal timing, a real result from logical effort theory, not an arbitrary heuristic. If an instance needs more gain because of increased output load, its input capacitance is increased to maintain the original gain, rather than just accepting a slower stage.
Technical Explanation
- During gain-based optimization, the algorithm computes the gain of each cell along the critical path and tries to maintain EQUAL gain for each stage -- this isn't an arbitrary heuristic, equal gain per stage is the actual optimal-timing result from logical effort theory.
- If an instance needs more gain because of increased output load, its INPUT capacitance is increased to maintain the original gain -- rather than accepting a slower stage or resizing in a way that would change the gain balance.
- Changing input capacitance (rather than the underlying drive strength directly) is what gives this technique wire-capacitance-load INDEPENDENCE -- the whole reason gain-based optimization became preferred over load-based optimization for deep submicron designs.
Common Mistake
The Trap: Assuming any resize that improves a slow stage's delay is equally good -- gain-based optimization specifically targets restoring EQUAL gain across stages, not just making one slow stage faster in isolation, because equal-gain is the actual condition for path-optimal timing.
Follow-up Question & Model Response
"Why would changing a cell's INPUT capacitance (rather than its output drive strength) be the key to wire-load independence?"
Candidate Model Response: Because input capacitance is a property of the cell itself, independent of what it's actually driving downstream -- adjusting it to restore gain keeps the delay model self-consistent regardless of the real wire load, whereas resizing based on an estimated wire-load model ties the result to an estimate that changes as real layout data becomes available, which is exactly the non-terminating iteration problem load-based optimization had.
Practical Example
Worked Example: A cell on the critical path sees increased output load from a nearby placement change. Gain-based optimization increases that cell's input capacitance (effectively upsizing it) specifically to restore its original gain relative to neighboring stages, keeping the whole path's gain balance -- and therefore its delay -- optimal.
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