Why did the industry shift from load-based to gain-based (logical effort) timing optimization for deep submicron designs specifically?

Short Answer

Load-based optimization approximates interconnect capacitance with a wire capacitance model, choosing cell drive strength from the estimated load -- fine when intrinsic delay dominated and wire resistance was low. As designs grew, synthesis using an estimated wire-load model could cause a NON-TERMINATING iterative process of resizing during timing closure, because the wire-load model no longer predicted actual wire lengths until physical design was complete. Gain-based optimization (logical effort) became preferred specifically because of load-independent cell delay -- it doesn't have this circular estimate-then-re-estimate problem.

Technical Explanation

• Load-based optimization approximates interconnect capacitance with a wire capacitance model, choosing cell drive strength from that estimated load -- this was adequate when intrinsic (gate) delay dominated total delay and wire resistance was low.
• As designs grew, the wire-load model no longer predicted actual wire lengths accurately until physical design was already complete -- creating a genuine chicken-and-egg problem: synthesis needs a load estimate to size cells, but the real load isn't known until layout exists.
• This could cause a NON-TERMINATING iterative process of resizing during timing closure -- each resize changes the design, which changes the real (but still estimated) load, which suggests another resize, without converging.
• A suggested fix within load-based optimization itself: use global routing information during load-based optimization, provided initial global and final detail routes correlate closely -- better, but still fundamentally estimate-dependent.
• Gain-based optimization (logical effort) became preferred for deep submicron BECAUSE of load-independent cell delay -- by working in terms of gain (electrical effort = Cl/Ci, a RATIO) rather than absolute load capacitance, it sidesteps the circular estimation problem entirely.

What To Check

• Warning sign: a legacy flow using load-based optimization on a modern, deep-submicron design shows timing closure that never seems to fully converge across successive resize iterations.
• Inspect: confirm whether gain-based (logical effort) optimization is actually being used, or whether the flow has inadvertently reverted to load-based sizing for some stage.
• Correct: ensure gain-based optimization governs cell sizing for deep-submicron designs specifically, given load-based optimization's documented non-termination risk at this scale.

Healthy, Suspicious & Hard-stop Results

• Expected: cell sizing converges within a bounded number of optimization iterations, consistent with gain-based (logical-effort) optimization's load-independent behavior.
• Investigate: cell sizing appears to oscillate or never fully converge across successive timing-closure iterations -- worth confirming gain-based optimization is actually in effect for the stage in question.
• Stop: a deep-submicron design relies on a load-based sizing methodology known to risk non-termination, with no plan to move to gain-based optimization.

What The Interviewer Is Testing

Whether you understand the STRUCTURAL reason for the load-based-to-gain-based shift (avoiding a genuine non-terminating iteration, not just "better accuracy"), and can state the real historical/technical motivation.