What causes a hold violation, and why can't slowing the clock fix it?

Short Answer

A hold violation means new data reaches the capture flop too soon after the clock edge, before the flop has safely stored the old value. It is caused by short data paths, a capture clock that arrives later than the launch clock, and fast process corners. Slowing the clock does not help because the hold check compares launch and capture on the same clock edge, so the period is not part of the equation.

Technical Explanation

• A flop needs its input stable for a short hold time after the capture edge. The hold check asks whether new data, launched by the same edge at the previous flop, could arrive inside that window and overwrite the value being captured.
• Hold slack is arrival time minus required time, where required time is the capture clock latency plus the library hold time plus uncertainty. The launch and capture edges are the same edge, so the period cancels out.
• This is why frequency does not matter. If a hold check fails at 1 GHz, it fails at 100 MHz as well. A hold failure on silicon cannot be screened out by running slower, which makes it more serious than a setup failure.
• Short data paths are the main cause: flop to flop with little or no logic between them, which is common in scan chains, shift registers and pipeline stages.
• Positive skew hurts hold. If the capture clock arrives later than the launch clock, the hold window moves later and fast data has a better chance of landing inside it. Skew that helps setup on one path is exactly what hurts hold on a short path to the same flop.
• Fast corners make hold worse. At the fast process, high voltage corner, cell and wire delays are smallest, so the data path is at its shortest. Hold is signed off at those corners, while setup is signed off at the slow ones.
• Derates work in reverse for hold: the data path and launch clock are derated early (fast) and the capture clock late. Crosstalk can also speed up a victim net when the aggressor switches the same way, reducing arrival time further.
• Hold is usually fixed after setup, by adding delay on the data path close to the capture flop. PrimeTime hold fixing with fix_eco_timing -type hold (PT) uses both sizing and buffer insertion by default and tries not to create setup or DRC violations.

Follow-up Question & Model Response

"Why is hold usually fixed after setup, and not before?"

Candidate Model Response: Setup fixing makes paths faster, which can create new hold violations, and the PrimeTime UG notes that setup fixing is allowed to introduce hold violations because setup is harder to fix. Hold fixing adds delay, and PrimeTime hold fixing preserves setup slack. If you fix hold first, the setup work that follows can undo it. Fixing setup first and hold second means each step leaves the earlier one in place. DRC fixing comes before both because it has the highest priority.