How do you check consistency across all input files?
From PDVerse PnR Interview Handbook, part of the pdVerse Mentor Guide
Last updated:
Short Answer
Checking each input file in isolation isn't enough — the real bugs live in the relationships between files, where each one is individually valid but they collectively describe different designs. Start with identity: does the top module, hierarchy, netlist revision, macro configuration, library release, and process/metal stack all point to the same intended design? A valid SDC for last week's netlist revision can be silently wrong for today's.
Technical Explanation
- Checking each input file in isolation isn't enough — the real bugs live in the relationships between files, where each one is individually valid but they collectively describe different designs.
- Start with identity: does the top module, hierarchy, netlist revision, macro configuration, library release, and process/metal stack all point to the same intended design? A valid SDC for last week's netlist revision can be silently wrong for today's.
- Then check interfaces: do cell and pin names, port widths, and power-pin expectations in the netlist actually match what SDC and UPF are trying to select? An SDC written against old port names leaves the current design underconstrained — no error, just silently missing constraints.
- Check physical consistency: database scale, LEF/DEF units, sites, rows, tracks, layers, vias, macro dimensions — a unit mismatch here (like DBU scale) doesn't fail loudly, it just produces wrong-by-a-constant-factor geometry.
- Check electrical consistency: library units, voltage/temperature coverage, RC models, layer mapping, and scenario assignment — never "fix" a unit mismatch by scaling numbers until the report looks familiar, that just papers over the real bug.
- Finally, cross-check reported statistics against upstream expectations: instance count, port count, unresolved references, clock count, macro count, scan annotation, power-domain membership. Checksums tell you a file didn't change; only these design-statistics comparisons tell you the right file was loaded in the right context.
Command Checks & Actions
check_design -checks {netlist unbound dp_pre_floorplan}Runs the selected design-readiness checks across the loaded inputs, the structural half of input consistency.
check_timingFinds missing or inconsistent timing setup -- the units/SDC-side half of input consistency that check_design does not cover.
report_ref_libsConfirms every reference library that should be attached actually is, catching a silently missing input before it shows up as a mysterious downstream error.
Common Mistake
The Trap: Accepting a package solely because all filenames share the same date or because there are no fatal parser errors.
Follow-up Question & Model Response
"Which mismatch is hardest to notice?"
Candidate Model Response: A plausible but wrong model or constraint can produce believable reports; cross-file manifests and coverage checks expose it.
Practical Example
Tapeout Scenario: A DEF uses 1000 units per micrometer, so a coordinate of 100000 represents 100 micrometers. Misinterpreting that number as micrometers creates a thousandfold error. Inspect the declared unit system and import result rather than guessing scale from large numbers.
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