IntermediateQuestion 86 of 84Source PDF page undefined

How do you audit output-delay constraints?

From PDVerse PnR Interview Handbook · pdVerse Mentor Guide

Short Answer

Verify receiving reference clock, edges, sign convention, min/max values, and whether the external requirement matches the interface specification.

Technical Explanation

For an output port, min and max describe the receiving device's early and late requirements relative to its reference clock.

What To Check

• Warning sign: Outputs have only setup-like max requirements or use the wrong virtual clock. • Inspect: Compare one named object across the related reports; the same object should tell a consistent story. • Correct: Correct the boundary budget at the source and inspect representative output timing paths.

Command Checks & Actions

• report_ports -output_delay [get_ports *]: shows boundary constraints and electrical assumptions • check_timing: finds missing or inconsistent timing setup Run the commands in order. Each line answers a separate part of the check.

Healthy, Suspicious & Hard-stop Results

• Expected: Verify receiving reference clock, edges, sign convention, min/max values, and whether the external requirement matches the interface specification. • Investigate: Outputs have only setup-like max requirements or use the wrong virtual clock. • Stop before floorplanning when required logic or timing coverage is missing or unexplained. Correct the boundary budget at the source and inspect representative output timing paths.

Common Mistake

Do not assume the check passed just because ICC2 continued: Outputs have only setup-like max requirements or use the wrong virtual clock. Fix or narrowly justify the named objects, then rerun the same command.

What The Interviewer Is Testing

Be ready to explain why this matters before floorplanning: Outputs have only setup-like max requirements or use the wrong virtual clock.

Follow-up Question & Model Response

Model response: “I would save the report, inspect one affected object in the correct block and scenario, and make or request this correction: Correct the boundary budget at the source and inspect representative output timing paths. Then I would reopen the clean checkpoint and rerun the same evidence.”

Practical Example

Symptom: Outputs have only setup-like max requirements or use the wrong virtual clock. Corrective path: Correct the boundary budget at the source and inspect representative output timing paths.

Original guide diagramHow do you audit output-delay constraints?
How do you audit output-delay constraints?, illustrating the physical design concept.