What mandatory checks define the Placement Signoff Gate before proceeding to Clock Tree Synthesis (CTS)?
From PDVerse PnR Interview Handbook · pdVerse Mentor Guide
Short Answer
Proceeding into CTS on an unverified or illegal placement is a guaranteed way to build an unroutable clock tree and blow timing closure downstream — this gate exists precisely to catch that before it becomes an expensive problem. Placement legality must be exactly zero across the board: zero unplaced instances, zero cell overlaps, zero off-grid instances, zero illegal orientation flips, and zero pin-access violations — "mostly clean" doesn't count here.
Technical Explanation
- Proceeding into CTS on an unverified or illegal placement is a guaranteed way to build an unroutable clock tree and blow timing closure downstream — this gate exists precisely to catch that before it becomes an expensive problem.
- Placement legality must be exactly zero across the board: zero unplaced instances, zero cell overlaps, zero off-grid instances, zero illegal orientation flips, and zero pin-access violations — "mostly clean" doesn't count here.
- Physical cell audits need full coverage: 100% well-tap rule coverage, 100% endcap row termination, and zero floating gate pins, confirmed via 100% tie-cell connectivity.
- High-fanout net synthesis and DRC need to be fully resolved before CTS: every non-clock high-fanout control net buffered within bounded fanout, and zero max-transition, max-capacitance, or max-fanout violations under the pre-CTS ideal-clock assumption.
- Finally, routing congestion and virtual (pre-CTS) timing need to be within budget: G-cell routing overflow under a tight threshold with no significant localized pockets, and normalized pre-CTS worst-negative-slack sitting within budgeted skew margins with zero unconstrained endpoints — because CTS is about to add real clock-tree delay on top of whatever margin is left here.
Common Mistake
The Trap: Proceeding to CTS with massive unbuffered reset nets or unresolved G-cell congestion. CTS will try to route high-priority clock trunks through congested channels, creating disastrous clock skew and unroutable detailed routing shorts.
Follow-up Question & Model Response
"What is the danger of leaving max-transition violations unresolved before CTS?"
Candidate Model Response: Slow transition times cause severe driver internal delay, excessive short-circuit power, and high susceptibility to crosstalk noise.
Practical Example
Placement Signoff Audit Script:
# Complete Placement Signoff Audit Gate
check_legality -verbose
check_tie_cells
check_tap_cell_density
report_constraints -all_violators -max_transition -max_capacitance
report_congestion -grc_based
report_qor -summaryPhysical Design & Planning Handbook
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