What optimization techniques does `place_opt` apply to close setup timing pre-CTS?
From PDVerse PnR Interview Handbook · pdVerse Mentor Guide
Short Answer
Pre-CTS optimization (place_opt) closes WNS and TNS setup slack by executing gate sizing (upsizing drive strength), buffer insertion (splitting long RC nets), logic restructuring (pin swapping, cloning/de-cloning), and multi-threshold voltage (Multi-Vt) swapping under ideal clock assumptions.
Technical Explanation
- Pre-CTS Timing Optimization (
place_opt) executes early timing closure on synthesized gate-level netlists under ideal clock assumptions, preparing the design for clock tree synthesis and routing. - Ideal Clock Environment: Pre-CTS timing operates with ideal clock distribution (0ps network latency) while budgeting realistic timing guardbands via
set_clock_uncertainty(e.g., 150ps) to account for anticipated post-CTS skew, jitter, and on-chip variation (OCV). - Gate Sizing & Drive Optimization: Dynamically up-sizes cell drive strengths on critical setup paths to accelerate capacitive charging, and down-sizes non-critical gates to recover silicon area and static leakage power.
- Interconnect Buffer Insertion: Inserts low-delay repeater buffers along long, high-RC interconnect wires to break quadratic delay scaling into linear delay segments.
- Logic Restructuring & Pin Swapping: Executes equivalent logical pin swapping (routing critical timing signals to the fastest input pins of complex logic gates), logic cloning (duplicating heavily-loaded gates to split fanout), and de-cloning.
- Multi-Threshold Voltage (Multi-Vt) Assignment: Selectively assigns low-Vt (LVT) and ultra-low-Vt (ULVT) cells along critical timing paths to maximize switching speed, while locking high-Vt (HVT) cells onto non-critical paths to minimize leakage current.
Common Mistake
The Trap: Allowing place_opt to insert buffers inside locked relative placement (RP) groups or hand-instantiated clock paths, breaking manual structural intent.
Follow-up Question & Model Response
"Why does place_opt optimize worst negative slack (WNS) before total negative slack (TNS)?"
Candidate Model Response: WNS defines maximum operating clock frequency. The optimizer focuses on the most critical paths first, then balances TNS across secondary violating endpoints.
Practical Example
Configuring place_opt Optimization Passes:
# Synopsys ICC2: Run comprehensive pre-CTS placement optimization
set_app_options -name opt.common.allow_swapping_pins -value true
set_app_options -name opt.leakage.effort -value high
place_opt -from initial_opto -to final_opto
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