Why does the recommended ECO order run power recovery, then DRC, then setup, then hold, then leakage recovery?
From PDVerse PnR Interview Handbook · pdVerse Mentor Guide
Short Answer
The order follows which step is allowed to hurt which. Power recovery goes first because it never creates a violation and frees room; DRC and noise come next because DRC fixing has the highest priority and may move setup and hold slack. Setup follows because it honours DRC but may spend hold margin, then hold, which honours both, and finally a leakage-only Vt swap that changes no layout.
Technical Explanation
- Table 66 of the PT UG lists four steps: power recovery by sizing and buffer removal, DRC and noise fixing, timing fixing, and a final leakage recovery by threshold voltage swapping.
- Setup and hold fixing do not degrade max capacitance and max transition, but DRC fixing can degrade setup and hold. Run DRC after timing and it would undo the timing work.
- Hold fixing preserves setup slack, but setup fixing may introduce hold violations. Run hold before setup and the setup pass reopens hold.
- Power recovery first never introduces or worsens a timing or DRC violation, and the area it frees helps the later fixes find room.
- The final leakage pass swaps threshold voltage only, with no layout change, so it cannot disturb placement once timing is closed.
- For large ECOs, the PT UG suggests running DRC, setup and hold one at a time to limit disturbance to ECO routing and legalization, starting with the type that causes more changes.
fix_eco_timing -ignore_drc(PT) reverses the priority for timing. By default timing is not fixed on paths with DRC violations; with the option, max transition, capacitance and fanout may be degraded.- Each pass ends with
write_changes(PT), implementation in ICC2, re-extraction and a fresh timing run before the next loop.
What To Check
- Violation counts of each type before every step.
- How far setup and hold moved during the DRC step.
- New hold violations created by the setup step.
- That the leakage step produced only same-footprint swaps.
Command Checks & Actions
report_constraint -all_violatorsDRC baseline before the ECO sequence.
fix_eco_powerStep 1: area and power recovery by sizing and buffer removal.
fix_eco_drc -type max_transition -methods {size_cell insert_buffer} -buffer_list {BUFX2 BUFX4}Step 2: DRC fixing, which may move setup and hold slack.
fix_eco_timing -type setupStep 3a: setup fixing, honouring DRC.
fix_eco_timing -type hold -buffer_list {BUFX2 DLY1X2}Step 3b: hold fixing, honouring setup and DRC.
fix_eco_power -pattern_priority {HVT LVT}Step 4: leakage recovery by Vt swap.
write_changes -format icctcl -output eco_all.tclWrites the change list for ICC2.
Healthy, Suspicious & Hard-stop Results
- Healthy (illustrative): Each step leaves the earlier results intact: DRC stays at zero through timing fixing and setup stays clean through hold fixing.
- Suspicious (illustrative): Hold fixing ends with more setup violations than it started with, which suggests a scenario missing from the command focus.
- Hard stop: A run with
-ignore_drcthat ends with new max transition violations and no DRC pass afterwards.
Common Mistake
The Trap: Fixing hold first because hold failures are fatal in silicon while setup only costs frequency. The later setup pass is allowed to spend hold margin, reopens 30 of the fixed hold paths, and the hold ECO has to be run and implemented twice.
What The Interviewer Is Testing
- Does the candidate explain the precedence rules behind the order, not only the order?
- Knowing when to split a large ECO into separate passes.
- Understanding what
-ignore_drctrades away.
Follow-up Question & Model Response
"When would you use -ignore_drc?"
Candidate Model Response: When a few critical timing paths are blocked because a DRC violation sits on them, since by default fix_eco_timing (PT) will not fix timing on those paths. With -ignore_drc the tool can fix them but may degrade max transition, capacitance and fanout. It is a late-stage option for specific paths and must be followed by a DRC pass. If that DRC pass undoes the timing fix, the path needs a manual change.
Practical Example
Tapeout Scenario: A routed block shows 210 max transition violations, setup WNS -35 ps over 90 endpoints and hold WNS -15 ps over 140 endpoints (illustrative). Step 1 downsizes 6,000 cells with no new violations. Step 2 clears all 210 DRC violations, but setup grows to 104 failing endpoints with WNS -38 ps. The setup pass clears all 104 and adds 12 hold violations, taking hold to 152. The hold pass clears all 152 with setup still clean, and step 4 swaps 22,000 cells to HVT with no layout change.
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