What is Relative Placement (RP), and when should it be used for datapath logic?
From PDVerse PnR Interview Handbook · pdVerse Mentor Guide
Short Answer
Analytical placement is great at scattering random control logic to minimize wirelength, but it's actually the wrong tool for a highly regular datapath — a 64-bit ALU's bit-0 through bit-63 all follow the identical structure, and letting the placer treat each bit independently scatters them unevenly, creating uneven wire delays and real clock skew. Relative Placement fixes this by letting the designer lock the datapath into an explicit matrix grid — say, 64 rows by 4 columns — with each instance assigned an exact relative row/column offset to its neighbors.
Technical Explanation
- Analytical placement is great at scattering random control logic to minimize wirelength, but it's actually the wrong tool for a highly regular datapath — a 64-bit ALU's bit-0 through bit-63 all follow the identical structure, and letting the placer treat each bit independently scatters them unevenly, creating uneven wire delays and real clock skew.
- Relative Placement fixes this by letting the designer lock the datapath into an explicit matrix grid — say, 64 rows by 4 columns — with each instance assigned an exact relative row/column offset to its neighbors.
- The whole RP group then moves as one rigid unit during global placement, the same way a macro would, so every bit's interconnect delay stays uniform instead of drifting bit to bit.
- The payoff shows up directly in timing closure and skew: predictable path delays, lower routing congestion because the structure is compact and regular, and reported area reductions up to about 20% versus letting an unconstrained placer handle the same datapath.
- Use RP specifically for structured, repeated datapath logic — ALUs, multipliers, FIFOs, register files — not for irregular control logic, where it would just add unnecessary constraint without benefit.
Common Mistake
The Trap: Creating an RP group that violates standard cell row site height or power rail abuttal rules, causing legalization to fail across the entire block.
Follow-up Question & Model Response
"Can RP groups contain hierarchical sub-modules?"
Candidate Model Response: Yes. Hierarchical RP groups allow sub-groups (e.g., 1-bit full adders) to be nested inside parent bit-slice arrays.
Practical Example
Creating a Relative Placement Group:
# Synopsys ICC2: Create a 32-bit ALU Relative Placement Group
create_rp_group RP_ALU -columns 4 -rows 32
for {set i 0} {$i < 32} {incr i} {
add_to_rp_group RP_ALU -leaf u_alu/reg_$i -column 0 -row $i
add_to_rp_group RP_ALU -leaf u_alu/add_$i -column 1 -row $i
}Physical Design & Planning Handbook
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