In what order do you try setup fixes, and why that order?

Short Answer

Start with the fix that costs least and disturbs the layout least, and climb only when the cheaper rung runs out. The usual order is Vt swap, cell sizing, buffering or fanout split, logic restructuring or cloning, useful skew, and finally placement or floorplan changes. Each step up moves more cells, touches more nets and puts more already-closed timing at risk, so you stop at the first rung that clears the path.

Technical Explanation

• Vt swap comes first because the footprint and pin positions stay the same, so nothing moves and no route changes. The price is leakage, which ICC2 lets you cap with set_multi_vth_constraint -low_vt_percentage 10 (ICC2), measured by cell count or by area through -cost.
• Set that LVT cap early, once the LVT cell group is declared with set_threshold_voltage_group_type -type low_vt (ICC2). ICC2 limits percentage-LVT optimization during route_opt (ICC2) to avoid disturbing QoR, so a block over budget at routing stays over.
• Sizing is next, with size_cell (PT) or size_cell (ICC2). A stronger cell loads the stage before it and may be wider, so legalization can shift neighbours. fix_eco_timing -type setup (PT) sizes only by default.
• Buffering and fanout splitting come third. Shielding a critical load or breaking a long wire fixes a slow transition that sizing cannot, but each new cell needs a free site and routing. PrimeTime inserts with insert_buffer (PT); ICC2 scripts normally use add_buffer (ICC2) or add_buffer_on_route (ICC2), though ICC2 also accepts insert_buffer (ICC2).
• Restructuring and cloning change the logic, such as moving a late signal nearer the output or duplicating a driver. Equivalence must be rerun, so this usually goes back to ICC2 optimization.
• Useful skew borrows time from the next stage by delaying the capture clock. It is cheap when that stage has slack, but every flop on the moved clock branch shifts. Clock-network fixing in PrimeTime (-cell_type clock_network) works only in the physically aware flow, which requires a PrimeTime-ADV license.
• Placement and floorplan changes sit at the top: best for long-wire paths, but they reopen routing and timing for everything nearby.
• The order bends to the path. A path dominated by wire delay gains almost nothing from a Vt swap, so you go straight to buffering or placement.

What To Check

• Per-stage cell delay, net delay and transition on the failing path, to see what dominates.
• LVT headroom left against the multi-Vt constraint.
• Hold slack on the same endpoints before and after, since setup fixing may create hold violations.
• Free sites near the path before choosing buffering.
• Setup slack of the next stage before relying on useful skew.

Healthy, Suspicious & Hard-stop Results

• Healthy (illustrative): Vt swap and sizing clear the path, LVT stays at 8% against a 10% cap, and hold slack on the same endpoints stays positive.
• Suspicious (illustrative): Setup clears but 40 new hold violations appear on the same endpoints, or LVT jumps from 6% to 14% in one pass.
• Hard stop: A path still fails by more than any cell change can recover after sizing and buffering, for example -180 ps at 1 GHz. That needs restructuring or placement, not more swaps.

What The Interviewer Is Testing

• Can the candidate rank fixes by cost and disturbance instead of just listing them?
• Knowledge that PT setup fixing sizes only by default and that ICC2 limits LVT optimization in route_opt (ICC2).
• A strong answer changes the order for a wire-dominated path.

Follow-up Question & Model Response

"Why is a Vt swap usually tried before upsizing?"

Candidate Model Response: A Vt swap keeps the same footprint and pin positions, so no cell moves and no route changes. Upsizing can make the cell wider and adds input capacitance on the previous stage, which may slow that stage and push neighbours during legalization. The cost of the swap is leakage, which you control with a percentage cap. Once the LVT budget is spent, sizing becomes the cheapest remaining step.