IntermediateQuestion 200 of 222Source: Synopsys ICC2 Implementation User Guide X-2025.06-SP2: Reading Blocks for Signoff Design Rule Checking and Setting Options for Signoff Design Rule Checking

Which cell views does `signoff_check_drc` read, and why can that hide errors?

From PDVerse PnR Interview Handbook · pdVerse Mentor Guide

By Tabish Iqbal · 9+ Years VLSI Physical Design Experience

Short Answer

By default signoff_check_drc (ICC2) reads the design view for the top-level block and standard cells, but only the pin information from the frame view for macros and I/O pads. The frame view is an abstraction, so shapes inside a macro that a top-level route could violate against are not there to check. You swap in real data through merged stream files, layout views or design views, in that order of precedence.

A precedence table for child-cell data in signoff DRC: merged stream files first, then layout views, then design views, then frame views, with what each view contains and a red note that the frame view default hides macro interior shapes. — Technical Reference DiagramWhich cell views does `signoff_check_drc` read, and why can that hide errors?

Technical Explanation

Default reading: design view for the top block and library cell instances, pins only from the frame view for macro cells and I/O pad cells.
signoff.check_drc.ignore_blockages_in_cells (ICC2) defaults to true, so frame-view routing blockages are ignored. Setting it to false reads blockages as well as pins, which is still an abstraction.
signoff.physical.merge_stream_files (ICC2) replaces the library data with GDSII or OASIS data for the cells in those files, except for libraries named in signoff.physical.merge_exclude_libraries (ICC2).
signoff.check_drc.read_layout_views (ICC2) reads the layout view, which matches the stream data but runs faster. Layout views are not in cell libraries by default; they must be saved during library preparation with lib.workspace.save_layout_views (ICC2).
Precedence for child cells: merged stream data, then layout views, then design views from signoff.check_drc.read_design_views (ICC2), then frame views. A cell with none of these and no frame view is ignored.
Fill data is read only if its timestamp is newer than the design view, the read_if_uptodate default. A stale fill view is silently skipped, so fill-to-route spacing errors are never checked and density is measured without the fill; set_app_options -name signoff.check_drc.fill_view_data -value read (ICC2) reads it regardless.
The tool reads on-disk data, so save_block (ICC2) comes before every run.

What To Check

Which macros are in the merged stream list or layout-view list, and which fall back to frame view.
That layout views were actually saved in the libraries you point at.
Whether fill was read, from the fill view timestamp against the design view.
Error counts near macro edges before and after switching to real data.

Command Checks & Actions

ICC2 (icc2_shell)set_app_options -name signoff.physical.merge_stream_files -value {stdcell.gds macro.oas}

Uses the real GDSII and OASIS data for the cells in those files instead of library views.

ICC2 (icc2_shell)set_app_options -name signoff.check_drc.read_layout_views -value {SRAM*}

Reads the layout view for matching reference cells instead of the frame view.

ICC2 (icc2_shell)set_app_options -name signoff.check_drc.ignore_blockages_in_cells -value false

Reads frame-view blockages as well as pins for macros and pads.

ICC2 (icc2_shell)save_block

Writes the current state to disk, since IC Validator reads the on-disk block.

ICC2 (icc2_shell)signoff_check_drc

Runs signoff DRC with the view settings above.

Healthy, Suspicious & Hard-stop Results

Healthy (illustrative): Every macro with a GDS or layout view is read with real data, and DRC counts near macro edges stay the same when you switch from frame views.
Suspicious (illustrative): Switching one SRAM from frame to layout view adds 30 spacing errors along its edge. The frame view was hiding them.
Hard stop: Signoff DRC is quoted as clean with all macros on frame views and no full-GDS run. That result does not cover the macro boundaries.

Common Mistake

The Trap: Setting signoff.check_drc.read_layout_views (ICC2) for all memories and assuming it worked. The libraries were prepared without saved layout views, so the tool read frame views and the run looked clean. Standalone IC Validator on the merged GDS found 210 violations along the memory edges.

What The Interviewer Is Testing

Knowledge of the default views and the four-level precedence.
Awareness that layout and design views must be saved during library preparation.
A strong answer mentions the fill timestamp rule.

Follow-up Question & Model Response

"Why not just read the design view for everything?"

Candidate Model Response: Design views are also not saved in cell libraries by default, so the option can quietly fall back to frame views. For big macros, full data also costs runtime and memory. The layout view gives the same geometry as the stream data with less runtime. Many teams merge real GDS only for macros whose edges carry routing, then run standalone IC Validator on the full GDS for final signoff.

Practical Example

Tapeout Scenario: A block with 22 macros reports 14 signoff DRCs with default views (illustrative). After merging macro GDS through signoff.physical.merge_stream_files (ICC2), the count rises to 96. The new 82 are M4 spacing and end-of-line errors where top-level routes pass within 40 nm of shapes inside 3 memories. Adding routing blockages over those edges and rerouting clears those 82 with real data, leaving the original 14 to fix as usual.

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