What is timing closure, and when is a design actually "closed"?

Short Answer

Timing closure is the loop of implementing, extracting, analyzing and fixing until every timing check passes in every scenario that matters. A design is closed when setup and hold both show WNS of zero or better and TNS of zero in every active scenario, the design rule checks are clean, and signal integrity has been included. That result has to come from PrimeTime on extracted parasitics, with analysis coverage checked so you know nothing was left untested.

Technical Explanation

• Closure is a loop, not a single run. You implement the block in ICC2, extract parasitics from the routed layout, run static timing analysis, fix what fails, and repeat. Each fix changes cells or wires, so each pass needs a fresh extraction and a fresh timing run before you can trust the numbers.
• The exit gate has two sides for timing. Setup (max delay) and hold (min delay) must both pass, and they usually fail in different corners. A block that is setup-clean at the slow corner but has hold violations at the fast corner is not closed.
• Every active scenario counts. With multi-mode multi-corner analysis, a scenario is a mode plus a corner. Closing only the worst setup scenario and assuming the others follow is how silicon comes back with a hold failure in test mode at a cold corner.
• Design rule values are part of closure. Max transition and max capacitance violations mean the library delay tables are being used outside their characterized range, so the timing numbers on those nets cannot be trusted even if slack looks positive. report_constraint (PT) lists them.
• Signal integrity must be switched on for the signoff run. Crosstalk adds delta delay that can slow a setup path or speed up a hold path. A report without SI can show positive slack on a path that fails once coupling is included.
• Signoff means PrimeTime on extracted parasitics. ICC2 timing during route_opt (ICC2) is close but uses its own delay calculation and optimization-oriented settings, so the numbers you sign off on come from PrimeTime reading the SPEF from the final layout.
• Coverage is the last check people forget. report_analysis_coverage (PT) shows how many timing checks were actually tested and which were untested because of missing clocks, constants or false paths. Zero violations with 20% of checks untested is not closure.
• Late fixes usually happen as ECOs. fix_eco_timing (PT) fixes the remaining paths, write_changes (PT) writes them out, ICC2 applies them, and the loop runs again until the gate passes.

Follow-up Question & Model Response

"If PrimeTime shows zero violations in every scenario, what else would you check before calling the block closed?"

Candidate Model Response: I would first check analysis coverage, because a path that is never timed cannot fail. Unclocked registers, constant-driven pins and overly broad false paths all hide checks. Then I would confirm the parasitics are from the final layout and that SI was enabled in every scenario. I would also check that max transition and max capacitance are clean, since timing on a net with a transition violation comes from extrapolated library data. Only when those hold do I treat zero violations as closure.