What is useful skew?
From PDVerse PnR Interview Handbook · pdVerse Mentor Guide
Short Answer
Useful skew is clock skew added on purpose to fix timing. Delaying the capture clock of a failing flop gives its incoming path more time, and takes the same amount from the path leaving that flop. It works when the next stage has spare slack to lend. ICC2 does this automatically with concurrent clock and data optimization.
Technical Explanation
- Normally CTS tries to deliver the clock to every flop at the same time. Useful skew deliberately makes some arrivals later or earlier to move timing slack between pipeline stages.
- A flop is the capture point of the stage before it and the launch point of the stage after it. Delaying its clock by 30 ps gives the incoming stage 30 ps more setup time and gives the outgoing stage 30 ps less.
- This only helps when the outgoing stage has slack to spare. If both stages are critical, skew moves the violation from one to the other.
- Hold moves the other way. A later clock on that flop reduces hold margin on its incoming paths, and because the same flop now launches later, hold margin on its outgoing paths grows. Check hold at the fast corner after any skew change.
- In ICC2 this is concurrent clock and data (CCD) optimization. The UG describes it as adjusting clock arrival times of registers using positive slack. It is enabled by default for
place_opt(ICC2) andclock_opt(ICC2), and forroute_opt(ICC2) you setroute_opt.flow.enable_ccd(ICC2) to true. - You can turn it off in clock_opt with
clock_opt.flow.enable_ccd(ICC2) set to false, and you can limit how far latencies are adjusted. - Skew applied in implementation shows up in PrimeTime as different clock network delays on the launch and capture sides of a report. When a path passes with a large skew credit, that credit has to survive every scenario.
- Useful skew is limited by the clock tree itself. Delaying a flop clock means adding buffers or longer routing on its clock branch, which costs clock power and adds another place for on-chip variation to act. Making a clock earlier is harder, because it means pulling that flop off a shared branch closer to the root. Large skew targets on many flops can make the clock tree bigger and harder to balance in other modes.
Common Mistake
The Trap: Adding useful skew to fix a setup path at the slow corner without checking hold at the fast corner. The capture clock was delayed by 60 ps, the setup path closed, and 35 short paths into the same flops failed hold by 20 to 45 ps. The hold ECO added 90 delay cells to a crowded region.
Follow-up Question & Model Response
"When would you not use useful skew to fix a setup violation?"
Candidate Model Response: I would avoid it when the next stage from that flop has no spare slack, because I would only move the violation. I would also avoid it on flops with many short incoming paths that are close to failing hold. Interfaces to other blocks or I/O need care too, since the other side may assume a fixed latency. In those cases data path fixes are safer. I would also think twice in a multi-mode design, because a skew that helps the functional mode may hurt a test or low-power mode that shares the same clock tree.
Practical Example
Tapeout Scenario: A three-flop pipeline FF1 to FF2 to FF3 runs on a 1.0 ns clock (illustrative). Stage 1 has setup slack -25 ps and stage 2 has +80 ps. Delaying the FF2 clock by 40 ps gives stage 1 slack of +15 ps and stage 2 slack of +40 ps. In the scenario used for the fix, the shortest path into FF2 had hold slack +55 ps, so the 40 ps later capture leaves it at +15 ps. The fix needs no data path change and no data path area, only a small change on one clock branch. At the fast corner, where data paths are shorter, the team reruns hold on every path into FF2 and FF3, and all stay positive, the tightest at +11 ps. Had stage 2 only had +20 ps to lend, the same 40 ps delay would have made it fail by -20 ps, and the right fix would have been on the stage 1 data path instead.
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