What is High-Fanout Net Synthesis (HFNS), and how does it differ from CTS?

Short Answer

HFNS builds balanced buffer/inverter trees for high-fanout non-clock control signals (asynchronous resets, scan-enables, chip enables) during placement to fix max-transition and max-capacitance DRC violations. Unlike CTS, HFNS focuses on slew compliance rather than skew balancing.

Technical Explanation

• High-Fanout Net Synthesis (HFNS) is a placement-phase optimization step that builds balanced buffer or inverter tree topologies for high-fanout non-clock control signals.
• Target Signals: Applies to global asynchronous reset nets (rst_n), scan-enable controls (SE), test mode selects, and chip enables that drive hundreds or thousands of register sink pins across the chip.
• Optimization Objective: HFNS drives transition slew and load capacitance compliance, inserting repeater trees to eliminate max_transition and max_capacitance design rule violations (DRCs) before detailed timing closure.
• HFNS vs Clock Tree Synthesis (CTS): CTS is dedicated strictly to synchronous clock networks and focuses on zero-skew balancing, low insertion delay, and symmetric tree synthesis with specialized clock repeaters and 2W2S non-default routing rules. HFNS focuses on slew compliance with minimal area and power overhead, tolerating arbitrary skew between sinks.
• Clock Exclusion: Clock nets are explicitly marked with set_ideal_network or dont_touch prior to placement so that HFNS never inserts standard buffers onto clock paths, which would destroy clock tree symmetry and distort duty cycles.

Follow-up Question & Model Response

"Why are clock nets explicitly excluded from HFNS?"

Candidate Model Response: If HFNS buffers clock nets, standard cell inverters with uncontrolled P/N asymmetric delays will introduce massive duty cycle distortion and unmanageable clock skew before CTS even runs.