IntermediateQuestion 68 of 112Source: Synopsys PrimeTime User Guide: Setting Multicycle Paths

How do you write a multicycle path exception for a datapath that only needs a new result every three cycles?

From PDVerse STA Mentor Guide · pdVerse Mentor Guide

By Tabish Iqbal · 9+ Years VLSI Physical Design Experience

Short Answer

set_multicycle_path -setup 3 -from ... -to ... (SDC) grants the path three clock cycles for its setup check instead of the default one. Because that also shifts the hold check by default, you pair it with set_multicycle_path -hold 2 -from ... -to ... on the same path to move the hold check back to right after the launch edge.

Technical Reference DiagramHow do you write a multicycle path exception for a datapath that only needs a new result every three cycles?
A waveform showing a multiplier launch edge with a 3-cycle setup window extending to the far capture edge, and a separate hold arrow pulled back with -hold 2 to sit immediately after the launch edge.

Technical Explanation

A datapath like a multi-cycle multiplier or a slow accumulator often only needs its result sampled once every few cycles, and the multicycle commands let the tool check exactly that.

  • -setup N sets the number of cycles for the setup relationship. set_multicycle_path -setup 3 -from [get_cells SRC] -to [get_cells DST] (SDC) tells the tool the path has three clock cycles, not one, to complete.
  • The hold relationship shifts automatically when you change setup. Every valid hold relationship is derived from the setup relationship, so raising -setup to 3 moves the checked hold edge later by default — almost never where the design actually needs it.
  • -hold moves the capture edge for the hold check back. The value you give -hold tells the tool how many clock cycles to move the hold check's capture edge backward from its default position.
  • PrimeTime's own rule ties the two together: the effective number of hold cycles equals the setup value minus one minus the hold value. With -setup 3 and -hold 2, that gives 3 − 1 − 2 = 0 hold cycles, putting the hold check back at the launch-adjacent edge.
  • Skipping the -hold command is the most common way this goes wrong. Leaving only -setup 3 in place means the tool checks hold three cycles later than the design intends, which can hide a real hold violation right after the launch edge.
  • The number automatically tracks the clock period. If the clock period changes later, the three-cycle budget scales with it, unlike a fixed-number set_max_delay value written for one specific period.

Common Mistake

The Trap: adding set_multicycle_path -setup 3 alone and assuming the hold check is automatically correct because the setup relationship now matches the design's real behavior.

  • A designer confirms the setup slack looks reasonable at three cycles and moves on, not realizing the hold check silently moved three cycles later too.
  • A real hold violation right after the launch edge — the one that would show up under the default single-cycle assumption — goes completely unreported, because the tool is now checking hold three cycles too late to catch it.

Follow-up Question & Model Response

After adding set_multicycle_path -setup 3 -hold 2 to a path, how would you verify the hold check landed exactly where you intended, right after the launch edge?

Candidate Model Response: I would run report_timing -delay_type min (PT) on that path and check the reported launch and capture edge times directly, rather than trusting the values alone. Using PrimeTime's rule — hold cycles equal the setup value minus one minus the hold value — I would expect 3 minus 1 minus 2, which is zero, meaning hold should land right after the launch edge. If the report showed a different relationship, I would recheck whether -hold was applied to the same -from/-to pair as -setup, since a mismatch between the two commands is a common way this fails to line up.

Practical Example

A pipelined multiplier in a 300MHz core (3.33ns period) produces a valid result only once every three clock cycles from MULT_OUT_REG to RESULT_REG. The team applies set_multicycle_path -setup 3 -from [get_cells MULT_OUT_REG] -to [get_cells RESULT_REG] (SDC), granting a 10ns setup budget instead of 3.33ns, followed by set_multicycle_path -hold 2 -from [get_cells MULT_OUT_REG] -to [get_cells RESULT_REG]. Using the hold-cycle formula, 3 − 1 − 2 = 0, report_timing -delay_type min (PT) confirms the hold check now sits at the edge immediately after launch, exactly matching the multiplier's real single-cycle hold requirement even though setup spans three cycles.

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Related STA questions

BeginnerWhat is a multicycle path?AdvancedWhy does setting only -setup 2 create a hold problem? Walk the edges.IntermediateWhat is a half-cycle path, and why does it need a multicycle exception?IntermediateWhy would you choose a multicycle path over a false path for a signal that changes slowly?