Level 2 · Construction & Debugging

Intermediate STA Interview Questions

Connect setup and hold math, clock behavior, exceptions, design rules, reporting, and practical debug.

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Connect setup and hold math, clock behavior, exceptions, design rules, reporting, and practical debug.

  1. 01 What actually happens, step by step, during a full setup check on a launch-to-capture path?Intermediate · A setup check makes sure data launched by one clock edge arrives at the capture flop with enough margin before the next active edge. The tool adds up everything that delays the data (clock-to-Q, logic delay), then compares it against the capture edge position adjusted for skew and uncertainty.
  2. 02 What actually happens, step by step, during a full hold check on a launch-to-capture path?Intermediate · A hold check guards against data racing through too fast and corrupting the previous value still needed at the capture flop. It compares the fastest possible data arrival (using minimum delays) against the hold time requirement plus skew and hold uncertainty on the same edge.
  3. 03 What is clock propagation, and what does set_propagated_clock actually change?Intermediate · Before layout, STA typically assumes an idealized clock (arriving everywhere at the same time, zero skew). set_propagated_clock switches the tool to compute the clock's actual insertion delay through the real, built clock tree once clock tree synthesis (CTS) has produced that physical network.
  4. 04 Why does forgetting set_propagated_clock after CTS make hold checks meaningless?Intermediate · Hold checks depend heavily on skew (S) between launch and capture clock arrival. If the clock is still treated as ideal after the real tree is built, every flop appears to receive the clock at t=0 — meaning skew is effectively zero in the tool's math, even though real skew exists in silicon.
  5. 05 What's the difference between clock uncertainty and clock jitter?Intermediate · Clock jitter is the clock edge itself wobbling cycle to cycle at its source — an inherent property of the clock generator. Clock uncertainty is a margin the timing tool is told to subtract from the setup/hold budget to account for jitter plus other unknowns (like unmodeled skew), and it is set explicitly via set_clock_uncertainty rather than measured directly from the tree.
  6. 06 What's the difference between clock source latency and clock network latency, and why model them separately before CTS?Intermediate · Source latency models the delay from the clock's true origin (such as an off-chip source or a PLL) to the point where the clock is defined in the design. Network latency models the estimated on-chip delay through the clock tree itself. Both are set with set_clock_latency as placeholders before a real clock tree physically exists.
  7. 07 How do you constrain a DDR-style interface where data needs both -clock and -clock_fall input delays?Intermediate · A DDR (double data rate) interface can launch or capture data on both clock edges, so a single input delay referencing only the rising edge isn't enough. -clock_fall tells the constraint to reference the falling edge instead, and both the rising and falling constraints need to coexist rather than overwrite one another.
  8. 08 Why is a false path dangerous if the "it can never happen" assumption turns out to be wrong?Intermediate · A false path is a path that STA can trace through the netlist topologically but that the engineer asserts can never actually be exercised in functional operation — for example, a path only active during a mode that never coexists with the capturing clock. set_false_path tells the tool to stop timing it entirely.
  9. 09 Why does a multicycle path need a matching -hold exception, and what happens if you forget it?Intermediate · set_multicycle_path relaxes the setup check to allow data more than one clock cycle to arrive, but it does not automatically move the hold check's reference edge. Without an explicit -hold exception, the hold check still defaults to checking against the very next edge (cycle 1), which is now the wrong edge relative to the relaxed setup capture edge.
  10. 10 What is the difference between asynchronous, logically_exclusive, and physically_exclusive clock groups?Intermediate · set_clock_groups classifies relationships between clock domains for timing (and sometimes crosstalk) purposes. -asynchronous marks clocks with no fixed phase relationship, so timing paths between them aren't meaningfully checked. logically_exclusive marks clocks that can never be functionally active at the same time, but which may still physically coexist on the die. -physically_exclusive goes further, marking clocks that also cannot physically interfere with each other. clk (p e rio d 1 0 0 0 ) clk_ d iv2 (p e rio d 2 0 0 0 , p h a se -lo cke d )
  11. 11 How do you define a generated clock correctly, and what goes wrong if you use create_clock instead on a divided clock?Intermediate · A generated clock is one derived from a master (or another generated) clock by on-chip logic — a divider, clock gate, multiplexer, or inversion. It must be defined with create_generated_clock so the tool understands and preserves its phase relationship to the source clock.
  12. 12 What are recovery and removal checks?Intermediate · Recovery and removal checks apply to asynchronous control signals like reset, verifying they're properly synchronized relative to the clock even though they aren't clocked data. A recovery check is setup-like: reset must be deasserted early enough before the active clock edge. A removal check is hold-like: reset must stay asserted long enough after the active clock edge.
  13. 13 What is a max_transition violation, and why is it treated as a design rule rather than a slack-based check?Intermediate · max_transition is a design-rule ceiling on the largest transition (slew/edge rate) time a cell input or output pin is allowed to see, independent of whether the path otherwise has positive timing slack. A violation is a hard DRC failure — it's checked against a libraryspecified limit, not against a computed slack margin.
  14. 14 What are max_capacitance limits, and is max_fanout also covered by these library references?Intermediate · max_capacitance is a design-rule ceiling in the standard cell library specifying the largest output load (capacitance) a cell or pin is allowed to drive, listed as a pin-group attribute in the liberty data alongside max_transition. Like max_transition, exceeding it is a DRC failure regardless of the path's slack.
  15. 15 What is timing-exception precedence, and why can a broad false path silently swallow an intended multicycle exception?Intermediate · When multiple timing exceptions could apply to the same path, the tool resolves them by precedence rather than combining them — and false path exceptions take precedence over multicycle exceptions. This means a broad false path declaration can completely exclude a path that an engineer separately intended to only relax via a multicycle exception.
  16. 16 What is the difference between graph-based analysis (GBA) and path-based analysis (PBA)?Intermediate · GBA keeps a single worst-case slew at each node in the timing graph and reuses that same value for every path passing through it — fast to compute, but pessimistic, since it can penalize a fast path with a slow, unrelated path's slew. PBA re-times each path individually using its own actual slews along the way — more accurate, but more computationally expensive since it can't be shared across paths.
  17. 17 How do you read the arc-by-arc breakdown in a report_timing output to find the dominant delay contributor?Intermediate · report_timing prints a Point/Incr/Path table walking down the launch path arc by arc, showing each cell or net's incremental delay and the running cumulative total. To find the dominant contributor, scan the Incr column for the single largest jump rather than just looking at the final cumulative arrival time.
  18. 18 What does check_timing report, and why must you run it before trusting any slack number?Intermediate · check_timing scans the design for constraint problems that would make timing analysis incomplete or wrong — things like flops with no clock, ports with no output or input delay, generated clocks whose source can't be found, and combinational loops. Under- constraint is silent: a design missing constraints can still produce a green (all-passing) report_timing that means nothing.
  19. 19 What is path grouping, and how does it help organize timing reports and optimization?Intermediate · group_path organizes timing paths into named groups — by clock, by endpoint type, or by custom criteria — so that reporting and optimization tools can treat different classes of paths distinctly rather than lumping everything together. Common groupings by startpoint/endpoint type include reg2reg, in2reg, reg2out, and in2out.
  20. 20 Walk through how you would debug a path that fails by a surprising amount using report_timing increments.Intermediate · Start by reading report_timing's Incr column arc by arc to find where delay accumulates unexpectedly. The decision point at each large increment is whether it's a net arc (a wire) or a cell arc (a gate): a big net increment points to a physical fix like rerouting, buffering, or placing cells closer together, while a big cell increment points to checking the driving input transition and load, then sizing or fixing the cell.