Walk through a full setup check including clock reconvergence pessimism (CRPR) — why does OCV derating create artificial pessimism on shared clock paths, and how is it removed?
From PDVerse STA Mentor Guide · pdVerse Mentor Guide
Technical Explanation
A full setup check compares data arrival against the required time, but when launch and capture clocks share a common trunk before diverging, applying OCV derates independently to each side double-counts variation on that shared segment.
Timing-path Reasoning
Arrival = launch clock edge + launch clock network delay + launching flop clock-to-Q + sum of data path cell/net delays. Required = capture clock edge (one period later for single-cycle) + capture clock network delay minus library setup time minus clock uncertainty, adjusted by any CRPR/CPPR credit. Clock skew is capture_clock_delay minus launch_clock_delay. If OCV derates the shared trunk slow for the late (capture) side and fast for the early (launch) side simultaneously, that trunk is being modeled as both slow and fast at once, which is physically impossible since it is the same physical wire and cells for both paths up to the branch point.
Equation
Arrival = launch clock edge + launch clock network delay + launching
flop clock-to-Q + Σ(data path cell and net delays); Required =
capture clock edge (one period later for single-cycle) + capture
clock network delay − library setup time − clock uncertainty (± any
CRPR/CPPR credit and derate effects); Clock skew =
capture_clock_delay − launch_clock_delay. Worked: arrival = 0 + 120
+ 90 + 690 = 900; required = 1000 + 150 - 60 - 40 + 15 = 1065; slack
= 1065 - 900 = +165 MET.Expected Result
CRPR computes the early/late delay difference on the shared clock segment up to the branch point and credits that difference back into the slack equation, so the reported slack reflects only the divergent-path variation.
Failure Symptoms
Without CRPR, setup slack is understated (falsely pessimistic) specifically on paths where launch and capture clocks share significant common clock tree before splitting to their respective flops.
Root Cause
Independent early/late derating applied to a physically shared clock segment, treating one wire as simultaneously fast and slow.
Mentor Note — Debugging Procedure
Trace the clock tree from root to both the launching and capturing flops, identify the branch point, and confirm the tool is crediting back the shared-segment delta rather than applying full derate spread on both sides. Setup checks with deep, sharing clock trees are not accurately signed off without CRPR — the credit is what separates real skew-driven risk from geometry-driven derate pessimism.
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