What goes wrong when a compound generated clock (divide-then-gate) is defined incorrectly, and how do you validate it?
From PDVerse STA Mentor Guide · pdVerse Mentor Guide
Technical Explanation
A compound generated clock — one that is both divided and gated from its source — must correctly encode both operations, or the tool will compute wrong edges, wrong periods, or misclassify the clock's relationship to other clocks in the design.
Timing-path Reasoning
The generated clock is still declared relative to a source (e.g., -source [get_ports CKP1]) with the divide ratio (-divide_by 2) applied at the point where the clock is captured (e.g., [get_pins U1/Q]). If gating logic sits between the divider and the rest of the clock tree, the generated clock definition must reflect the point after both operations have occurred, otherwise the derived clock's edges will not match silicon behavior, and downstream logic sees an incorrect frequency or duty cycle relative to its actual source.
Command
create_generated_clock -source [get_ports CKP1] -divide_by 2 [get_pins U1/
Q]Switch-by-switch
-source identifies the upstream reference clock the compound generated clock derives
from. -divide_by 2 establishes the frequency ratio at the generated point, which must be
defined at the correct pin representing the true post-divide (and post-gate) clock signal.Expected Result
The generated clock's edges and period correctly reflect the actual divided-and-gated waveform, so all downstream timing paths referencing this clock are checked against the real capture/launch behavior.
Failure Symptoms
Incorrect definition manifests as timing paths being checked against the wrong period or wrong active edges, potentially masking real violations or reporting false ones on paths downstream of the compound clock.
Root Cause
The generated clock declaration not accurately capturing the combined divide-then-gate transformation applied to the source clock before it reaches the rest of the design.
Mentor Note — Debugging Procedure
Confirm the generated clock is defined at the pin that reflects the final post-divide/ post-gate waveform, and cross-check the resulting clock's period and edges against the intended hardware behavior using clock relationship/skew reporting. A compound generated clock is only as trustworthy as the pin and divide ratio chosen to define it — validate that the declared clock point matches the true post-transformation waveform before trusting any downstream timing report.
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