IntermediateQuestion 71 of 112Source: Synopsys PrimeTime User Guide: Derating Timing Delays

What is a derate factor, and how do early and late derates apply to opposite sides of a setup check?

From PDVerse STA Mentor Guide · pdVerse Mentor Guide

By Tabish Iqbal · 9+ Years VLSI Physical Design Experience

Short Answer

A derate factor is a multiplier the tool applies to a calculated delay to model manufacturing and environmental variation the delay calculation alone cannot see. set_timing_derate -early (SDC) scales delays down to model a faster-than-nominal path, and -late scales them up to model a slower-than-nominal path, and a single setup check actually uses both at once on opposite sides of the same path.

A setup check diagram with the launch clock path and data path scaled up by a late derate arrow and the capture clock path scaled down by an early derate arrow, narrowing the setup window between them. — Technical Reference DiagramWhat is a derate factor, and how do early and late derates apply to opposite sides of a setup check?

Technical Explanation

On-chip variation mode does not apply one derate to a whole check — it applies early derating and late derating to different parts of the same check at the same time.

The factor itself is a plain multiplier. set_timing_derate -late 1.2 (SDC) increases every affected cell and net delay by 20%; set_timing_derate -early 0.9 decreases them by 10%. Values above 1.0 make delays worse, values below 1.0 make them better.
A setup check wants the worst-case gap between launch and capture. For a setup check, the tool applies late derating to the launch clock path and the data path, since a slower launch or slower data makes setup harder to meet.
The capture clock path gets early derating on the same setup check. A faster capture clock path brings the capture edge earlier, tightening the setup window from the other side, so the tool derates that side of the clock tree in the opposite direction.
Hold checks flip the assignment. For a hold check, the tool applies early derating to the launch side and late derating to the capture clock path, since a hold violation is worst when data arrives too soon and the capture clock arrives too late.
This dual application is what "on-chip variation mode" means. Turning on set_timing_derate at all implicitly switches the tool into this mode, similar to set_operating_conditions -analysis_type on_chip_variation (SDC), rather than derating being a simple flat penalty on every number.
You must specify -early or -late separately. A single set_timing_derate command cannot set both at once; two separate commands are required to define the full early-and-late picture.

Common Mistake

The Trap: thinking of a derate factor as one penalty applied uniformly to a path's total delay, rather than a targeted adjustment applied differently to the launch side and the capture side.

A designer sets only set_timing_derate -late 1.1 expecting it to make every check more conservative on its own.
Without the matching -early command on the capture clock side, the setup check only gets half of the intended margin, understating how much on-chip variation could actually widen the setup window.

Follow-up Question & Model Response

A report shows a setup path's launch clock path being derated by 1.1x while its capture clock path is derated by 0.9x, even though both paths use the same clock tree. Is that a bug?

Candidate Model Response: No, that is the expected behavior of on-chip variation mode, not a bug. Even though the launch and capture clock paths share the same physical clock tree up to a point, the tool treats them as two independent sides of one setup check: the launch side gets late derating because a slower launch clock makes setup harder, and the capture side gets early derating because a faster capture clock also makes setup harder, by arriving too soon. Applying opposite derates to the two sides is exactly how the tool models the worst realistic combination of variation across the two clock paths for that specific check.

Practical Example

A design applies set_timing_derate -early 0.92 and set_timing_derate -late 1.08 (SDC) for on-chip variation. On a setup check between FF_A and FF_B sharing a clock tree, report_timing -derate (PT) shows the launch clock path and data path scaled by 1.08, while the capture clock path is scaled by 0.92 on the very same report line. The combined effect narrows the setup window by roughly 16% compared to a nominal, non-derated check, even though only two commands were written.

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